[llvm] r229845 - [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator

[Jozef Kolek]

Author: jkolek
Date: Thu Feb 19 05:51:32 2015
New Revision: 229845

URL: http://llvm.org/viewvc/llvm-project?rev=229845&view=rev
Log:
[mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generator

Differential Revision: http://reviews.llvm.org/D7611

Added:
    llvm/trunk/test/CodeGen/Mips/micromips-and16.ll
    llvm/trunk/test/CodeGen/Mips/micromips-or16.ll
    llvm/trunk/test/CodeGen/Mips/micromips-xor16.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=229845&r1=229844&r2=229845&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Feb 19 05:51:32 2015
@@ -1154,12 +1154,14 @@ def ADD   : MMRel, ArithLogicR<"add", GP
 def SUB   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
 def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
 def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
+let AdditionalPredicates = [NotInMicroMips] in {
 def AND   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
             ADD_FM<0, 0x24>;
 def OR    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
             ADD_FM<0, 0x25>;
 def XOR   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
             ADD_FM<0, 0x26>;
+}
 def NOR   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
 
 /// Shift Instructions

Added: llvm/trunk/test/CodeGen/Mips/micromips-and16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-and16.ll?rev=229845&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-and16.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-and16.ll Thu Feb 19 05:51:32 2015
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* %b, align 4
+  %1 = load i32* %c, align 4
+  %and = and i32 %0, %1
+  store i32 %and, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: and16

Added: llvm/trunk/test/CodeGen/Mips/micromips-or16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-or16.ll?rev=229845&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-or16.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-or16.ll Thu Feb 19 05:51:32 2015
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* %b, align 4
+  %1 = load i32* %c, align 4
+  %or = or i32 %0, %1
+  store i32 %or, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: or16

Added: llvm/trunk/test/CodeGen/Mips/micromips-xor16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-xor16.ll?rev=229845&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-xor16.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-xor16.ll Thu Feb 19 05:51:32 2015
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* %b, align 4
+  %1 = load i32* %c, align 4
+  %xor = xor i32 %0, %1
+  store i32 %xor, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: xor16