[llvm] r229694 - This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.
Kit Barton
kbarton at ca.ibm.com
Wed Feb 18 08:21:47 PST 2015
Author: kbarton
Date: Wed Feb 18 10:21:46 2015
New Revision: 229694
URL: http://llvm.org/viewvc/llvm-project?rev=229694&view=rev
Log:
This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.
Phabricator review: http://reviews.llvm.org/D7616
Commiting on Nemanja's behalf.
Added:
llvm/trunk/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll
Modified:
llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
llvm/trunk/test/MC/PowerPC/vsx.s
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=229694&r1=229693&r2=229694&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Wed Feb 18 10:21:46 2015
@@ -970,7 +970,6 @@ def VPOPCNTD : VXForm_2<1987, (outs vrrc
[(set v2i64:$vD, (ctpop v2i64:$vB))]>;
let isCommutable = 1 in {
-let AddedComplexity = 500 in {
// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the
// VSX equivalents. We need to fix this up at some point. Two possible
// solutions for this problem:
@@ -991,6 +990,5 @@ def VORC : VXForm_1<1348, (outs vrrc:$vD
"vorc $vD, $vA, $vB", IIC_VecGeneral,
[(set v4i32:$vD, (or v4i32:$vA,
(vnot_ppc v4i32:$vB)))]>;
-} // AddedComplexity = 500
} // isCommutable
} // end HasP8Altivec
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=229694&r1=229693&r2=229694&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Wed Feb 18 10:21:46 2015
@@ -940,3 +940,28 @@ def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A,
} // AddedComplexity
} // HasVSX
+// The following VSX instructions were introduced in Power ISA 2.07
+/* FIXME: if the operands are v2i64, these patterns will not match.
+ we should define new patterns or otherwise match the same patterns
+ when the elements are larger than i32.
+*/
+def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
+let Predicates = [HasP8Vector] in {
+let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
+let isCommutable = 1 in {
+ def XXLEQV : XX3Form<60, 186,
+ (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
+ [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>;
+ def XXLNAND : XX3Form<60, 178,
+ (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
+ [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
+ v4i32:$XB)))]>;
+ } // isCommutable
+def XXLORC : XX3Form<60, 170,
+ (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+ "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
+ [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
+} // AddedComplexity = 500
+} // HasP8Vector
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll?rev=229694&r1=229693&r2=229694&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll Wed Feb 18 10:21:46 2015
@@ -1,6 +1,5 @@
; Check the miscellaneous logical vector operations added in P8
;
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
; Test x eqv y
define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
Added: llvm/trunk/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll?rev=229694&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll Wed Feb 18 10:21:46 2015
@@ -0,0 +1,52 @@
+; Check the miscellaneous logical vector operations added in P8
+;
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; Test x eqv y
+define <4 x i32> @test_xxleqv(<4 x i32> %x, <4 x i32> %y) nounwind {
+ %tmp = xor <4 x i32> %x, %y
+ %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
+ ret <4 x i32> %ret_val
+; CHECK: xxleqv 34, 34, 35
+}
+
+; Test x xxlnand y
+define <4 x i32> @test_xxlnand(<4 x i32> %x, <4 x i32> %y) nounwind {
+ %tmp = and <4 x i32> %x, %y
+ %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
+ ret <4 x i32> %ret_val
+; CHECK: xxlnand 34, 34, 35
+}
+
+; Test x xxlorc y
+define <4 x i32> @test_xxlorc(<4 x i32> %x, <4 x i32> %y) nounwind {
+ %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
+ %ret_val = or <4 x i32> %x, %tmp
+ ret <4 x i32> %ret_val
+; CHECK: xxlorc 34, 34, 35
+}
+
+; Test x eqv y
+define <8 x i16> @test_xxleqvv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+ %tmp = xor <8 x i16> %x, %y
+ %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ ret <8 x i16> %ret_val
+; CHECK: xxleqv 34, 34, 35
+}
+
+; Test x xxlnand y
+define <8 x i16> @test_xxlnandv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+ %tmp = and <8 x i16> %x, %y
+ %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ ret <8 x i16> %ret_val
+; CHECK: xxlnand 34, 34, 35
+}
+
+; Test x xxlorc y
+define <8 x i16> @test_xxlorcv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+ %tmp = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+ %ret_val = or <8 x i16> %x, %tmp
+ ret <8 x i16> %ret_val
+; CHECK: xxlorc 34, 34, 35
+}
+
Modified: llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt?rev=229694&r1=229693&r2=229694&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt (original)
+++ llvm/trunk/test/MC/Disassembler/PowerPC/vsx.txt Wed Feb 18 10:21:46 2015
@@ -404,6 +404,15 @@
# CHECK: xxland 7, 63, 27
0xf0 0xff 0xdc 0x14
+# CHECK: xxleqv 7, 63, 27
+0xf0 0xff 0xdd 0xd4
+
+# CHECK: xxlnand 7, 63, 27
+0xf0 0xff 0xdd 0x94
+
+# CHECK: xxlorc 7, 63, 27
+0xf0 0xff 0xdd 0x54
+
# CHECK: xxlandc 7, 63, 27
0xf0 0xff 0xdc 0x54
Modified: llvm/trunk/test/MC/PowerPC/vsx.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/PowerPC/vsx.s?rev=229694&r1=229693&r2=229694&view=diff
==============================================================================
--- llvm/trunk/test/MC/PowerPC/vsx.s (original)
+++ llvm/trunk/test/MC/PowerPC/vsx.s Wed Feb 18 10:21:46 2015
@@ -403,6 +403,15 @@
# CHECK-BE: xxland 7, 63, 27 # encoding: [0xf0,0xff,0xdc,0x14]
# CHECK-LE: xxland 7, 63, 27 # encoding: [0x14,0xdc,0xff,0xf0]
xxland 7, 63, 27
+# CHECK-BE: xxleqv 7, 63, 27 # encoding: [0xf0,0xff,0xdd,0xd4]
+# CHECK-LE: xxleqv 7, 63, 27 # encoding: [0xd4,0xdd,0xff,0xf0]
+ xxleqv 7, 63, 27
+# CHECK-BE: xxlnand 7, 63, 27 # encoding: [0xf0,0xff,0xdd,0x94]
+# CHECK-LE: xxlnand 7, 63, 27 # encoding: [0x94,0xdd,0xff,0xf0]
+ xxlnand 7, 63, 27
+# CHECK-BE: xxlorc 7, 63, 27 # encoding: [0xf0,0xff,0xdd,0x54]
+# CHECK-LE: xxlorc 7, 63, 27 # encoding: [0x54,0xdd,0xff,0xf0]
+ xxlorc 7, 63, 27
# CHECK-BE: xxlandc 7, 63, 27 # encoding: [0xf0,0xff,0xdc,0x54]
# CHECK-LE: xxlandc 7, 63, 27 # encoding: [0x54,0xdc,0xff,0xf0]
xxlandc 7, 63, 27
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