[llvm] r229675 - [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

[Vasileios Kalintiris]

Author: vkalintiris
Date: Wed Feb 18 08:57:05 2015
New Revision: 229675

URL: http://llvm.org/viewvc/llvm-project?rev=229675&view=rev
Log:
[mips] Avoid redundant sign extension of the result of binary bitwise instructions.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7581

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
    llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
    llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=229675&r1=229674&r2=229675&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Feb 18 08:57:05 2015
@@ -486,6 +486,14 @@ def : MipsPat<(trunc (assertzext GPR64:$
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
 
+// Bypass trunc nodes for bitwise ops.
+def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;

Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll?rev=229675&r1=229674&r2=229675&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll Wed Feb 18 08:57:05 2015
@@ -51,10 +51,7 @@ define signext i32 @and_i32(i32 signext
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; GP32:         and     $2, $4, $5
-
-  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          and     $2, $4, $5
 
   %r = and i32 %a, %b
   ret i32 %r

Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll?rev=229675&r1=229674&r2=229675&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll Wed Feb 18 08:57:05 2015
@@ -51,11 +51,7 @@ define signext i32 @or_i32(i32 signext %
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
-
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
-  ; FIXME: The sll instruction below is redundant.
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          or     $2, $4, $5
 
   %r = or i32 %a, %b
   ret i32 %r

Modified: llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll?rev=229675&r1=229674&r2=229675&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll Wed Feb 18 08:57:05 2015
@@ -51,10 +51,7 @@ define signext i32 @xor_i32(i32 signext
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; GP32:         xor     $2, $4, $5
-
-  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          xor     $2, $4, $5
 
   %r = xor i32 %a, %b
   ret i32 %r