[PATCH] R600/SI: Don't set isCodeGenOnly = 1 on all instructions
Tom Stellard
thomas.stellard at amd.com
Tue Feb 17 16:40:21 PST 2015
We only need to set this on pseudo instructions which won't
be used by the assembler.
---
lib/Target/R600/AMDGPUInstructions.td | 2 --
lib/Target/R600/R600Instructions.td | 5 +++++
lib/Target/R600/SIInstrFormats.td | 1 -
lib/Target/R600/SIInstrInfo.td | 16 ++++++++++++++--
4 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td
index 1c5f76d..8b5fe8c 100644
--- a/lib/Target/R600/AMDGPUInstructions.td
+++ b/lib/Target/R600/AMDGPUInstructions.td
@@ -23,8 +23,6 @@ class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instructio
let Pattern = pattern;
let Itinerary = NullALU;
- let isCodeGenOnly = 1;
-
let TSFlags{63} = isRegisterLoad;
let TSFlags{62} = isRegisterStore;
}
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index cf6ac48..08e3d51 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -580,6 +580,7 @@ i32imm:$COUNT, i32imm:$Enabled),
let ALT_CONST = 0;
let WHOLE_QUAD_MODE = 0;
let BARRIER = 1;
+ let isCodeGenOnly = 1;
let UseNamedOperandTable = 1;
let Inst{31-0} = Word0;
@@ -642,6 +643,7 @@ def FETCH_CLAUSE : AMDGPUInst <(outs),
field bits<8> Inst;
bits<8> num;
let Inst = num;
+ let isCodeGenOnly = 1;
}
def ALU_CLAUSE : AMDGPUInst <(outs),
@@ -649,10 +651,13 @@ def ALU_CLAUSE : AMDGPUInst <(outs),
field bits<8> Inst;
bits<8> num;
let Inst = num;
+ let isCodeGenOnly = 1;
}
def LITERALS : AMDGPUInst <(outs),
(ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > {
+ let isCodeGenOnly = 1;
+
field bits<64> Inst;
bits<32> literal1;
bits<32> literal2;
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
index 7b4031f..583f9fe 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -252,7 +252,6 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
- let isCodeGenOnly = 0;
let SALU = 1;
let SOPP = 1;
diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
index 1ca1f9f..dd3124b 100644
--- a/lib/Target/R600/SIInstrInfo.td
+++ b/lib/Target/R600/SIInstrInfo.td
@@ -363,7 +363,7 @@ class EXPCommon : InstSI<
multiclass EXP_m {
- let isPseudo = 1 in {
+ let isPseudo = 1, isCodeGenOnly = 1 in {
def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
}
@@ -380,6 +380,7 @@ class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SOP1 <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
@@ -438,6 +439,7 @@ class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
SOP2<outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
let Size = 4;
}
@@ -513,6 +515,7 @@ class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SOPK <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
@@ -555,6 +558,7 @@ class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SMRD <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
@@ -808,6 +812,7 @@ class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
VOP <opName>,
SIMCInstr <opName#"_e32", SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
@@ -834,6 +839,7 @@ class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
VOP <opName>,
SIMCInstr<opName#"_e32", SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
@@ -883,6 +889,7 @@ class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
VOP <opName>,
SIMCInstr<opName#"_e64", SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
@@ -1038,7 +1045,7 @@ multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
// An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
string asm, list<dag> pattern = []> {
- let isPseudo = 1 in {
+ let isPseudo = 1, isCodeGenOnly = 1 in {
def "" : VOPAnyCommon <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE>;
}
@@ -1187,6 +1194,7 @@ class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
VOP <opName>,
SIMCInstr<opName#"_e32", SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
@@ -1389,6 +1397,7 @@ class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
VINTRPCommon <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
@@ -1424,6 +1433,7 @@ class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
DS <outs, ins, "", pattern>,
SIMCInstr <opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
@@ -1641,6 +1651,7 @@ class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
MTBUF <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
}
class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
@@ -1711,6 +1722,7 @@ class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
MUBUF <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
+ let isCodeGenOnly = 1;
// dummy fields, so that we can use let statements around multiclasses
bits<1> offen;
--
2.0.4
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