[llvm] r229457 - [PowerPC] Support non-direct-sub/superclass VSX copies

Hal Finkel hfinkel at anl.gov
Mon Feb 16 15:46:31 PST 2015


Author: hfinkel
Date: Mon Feb 16 17:46:30 2015
New Revision: 229457

URL: http://llvm.org/viewvc/llvm-project?rev=229457&view=rev
Log:
[PowerPC] Support non-direct-sub/superclass VSX copies

Our register allocation has become better recently, it seems, and is now
starting to generate cross-block copies into inflated register classes. These
copies are not transformed into subregister insertions/extractions by the
PPCVSXCopy class, and so need to be handled directly by
PPCInstrInfo::copyPhysReg. The code to do this was *almost* there, but not
quite (it was unnecessarily restricting itself to only the direct
sub/super-register-class case (not copying between, for example, something in
VRRC and the lower-half of VSRC which are super-registers of F8RC).

Triggering this behavior manually is difficult; I'm including two
bugpoint-reduced test cases from the test suite.

Added:
    llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll
    llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy2.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=229457&r1=229456&r2=229457&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Mon Feb 16 17:46:30 2015
@@ -699,7 +699,7 @@ void PPCInstrInfo::copyPhysReg(MachineBa
   // legalization. Promote them here.
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   if (PPC::F8RCRegClass.contains(DestReg) &&
-      PPC::VSLRCRegClass.contains(SrcReg)) {
+      PPC::VSRCRegClass.contains(SrcReg)) {
     unsigned SuperReg =
       TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
 
@@ -708,7 +708,7 @@ void PPCInstrInfo::copyPhysReg(MachineBa
 
     DestReg = SuperReg;
   } else if (PPC::VRRCRegClass.contains(DestReg) &&
-             PPC::VSHRCRegClass.contains(SrcReg)) {
+             PPC::VSRCRegClass.contains(SrcReg)) {
     unsigned SuperReg =
       TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
 
@@ -717,7 +717,7 @@ void PPCInstrInfo::copyPhysReg(MachineBa
 
     DestReg = SuperReg;
   } else if (PPC::F8RCRegClass.contains(SrcReg) &&
-             PPC::VSLRCRegClass.contains(DestReg)) {
+             PPC::VSRCRegClass.contains(DestReg)) {
     unsigned SuperReg =
       TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
 
@@ -726,7 +726,7 @@ void PPCInstrInfo::copyPhysReg(MachineBa
 
     SrcReg = SuperReg;
   } else if (PPC::VRRCRegClass.contains(SrcReg) &&
-             PPC::VSHRCRegClass.contains(DestReg)) {
+             PPC::VSRCRegClass.contains(DestReg)) {
     unsigned SuperReg =
       TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
 

Added: llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll?rev=229457&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy1.ll Mon Feb 16 17:46:30 2015
@@ -0,0 +1,133 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+ at ub = external global [1024 x i32], align 4
+ at uc = external global [1024 x i32], align 4
+
+; Function Attrs: noinline nounwind
+define void @_Z8example9Pj() #0 {
+entry:
+  br label %vector.body
+
+; CHECK-LABEL: @_Z8example9Pj
+; CHECK: xxlor
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %43, %vector.body ]
+  %vec.phi20 = phi <4 x i32> [ zeroinitializer, %entry ], [ %44, %vector.body ]
+  %vec.phi21 = phi <4 x i32> [ zeroinitializer, %entry ], [ %45, %vector.body ]
+  %vec.phi23 = phi <4 x i32> [ zeroinitializer, %entry ], [ %46, %vector.body ]
+  %vec.phi24 = phi <4 x i32> [ zeroinitializer, %entry ], [ %47, %vector.body ]
+  %vec.phi25 = phi <4 x i32> [ zeroinitializer, %entry ], [ %48, %vector.body ]
+  %vec.phi26 = phi <4 x i32> [ zeroinitializer, %entry ], [ %49, %vector.body ]
+  %vec.phi27 = phi <4 x i32> [ zeroinitializer, %entry ], [ %50, %vector.body ]
+  %vec.phi28 = phi <4 x i32> [ zeroinitializer, %entry ], [ %51, %vector.body ]
+  %vec.phi29 = phi <4 x i32> [ zeroinitializer, %entry ], [ %52, %vector.body ]
+  %vec.phi30 = phi <4 x i32> [ zeroinitializer, %entry ], [ %53, %vector.body ]
+  %wide.load32 = load <4 x i32>* null, align 4
+  %.sum82 = add i64 %index, 24
+  %0 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum82
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load36 = load <4 x i32>* %1, align 4
+  %wide.load37 = load <4 x i32>* undef, align 4
+  %.sum84 = add i64 %index, 32
+  %2 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum84
+  %3 = bitcast i32* %2 to <4 x i32>*
+  %wide.load38 = load <4 x i32>* %3, align 4
+  %.sum85 = add i64 %index, 36
+  %4 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum85
+  %5 = bitcast i32* %4 to <4 x i32>*
+  %wide.load39 = load <4 x i32>* %5, align 4
+  %6 = getelementptr [1024 x i32]* @ub, i64 0, i64 undef
+  %7 = bitcast i32* %6 to <4 x i32>*
+  %wide.load40 = load <4 x i32>* %7, align 4
+  %.sum87 = add i64 %index, 44
+  %8 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum87
+  %9 = bitcast i32* %8 to <4 x i32>*
+  %wide.load41 = load <4 x i32>* %9, align 4
+  %10 = getelementptr inbounds [1024 x i32]* @uc, i64 0, i64 %index
+  %11 = bitcast i32* %10 to <4 x i32>*
+  %wide.load42 = load <4 x i32>* %11, align 4
+  %.sum8889 = or i64 %index, 4
+  %12 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum8889
+  %13 = bitcast i32* %12 to <4 x i32>*
+  %wide.load43 = load <4 x i32>* %13, align 4
+  %.sum9091 = or i64 %index, 8
+  %14 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum9091
+  %15 = bitcast i32* %14 to <4 x i32>*
+  %wide.load44 = load <4 x i32>* %15, align 4
+  %.sum94 = add i64 %index, 16
+  %16 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum94
+  %17 = bitcast i32* %16 to <4 x i32>*
+  %wide.load46 = load <4 x i32>* %17, align 4
+  %.sum95 = add i64 %index, 20
+  %18 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum95
+  %19 = bitcast i32* %18 to <4 x i32>*
+  %wide.load47 = load <4 x i32>* %19, align 4
+  %20 = getelementptr [1024 x i32]* @uc, i64 0, i64 undef
+  %21 = bitcast i32* %20 to <4 x i32>*
+  %wide.load48 = load <4 x i32>* %21, align 4
+  %.sum97 = add i64 %index, 28
+  %22 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum97
+  %23 = bitcast i32* %22 to <4 x i32>*
+  %wide.load49 = load <4 x i32>* %23, align 4
+  %.sum98 = add i64 %index, 32
+  %24 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum98
+  %25 = bitcast i32* %24 to <4 x i32>*
+  %wide.load50 = load <4 x i32>* %25, align 4
+  %.sum99 = add i64 %index, 36
+  %26 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum99
+  %27 = bitcast i32* %26 to <4 x i32>*
+  %wide.load51 = load <4 x i32>* %27, align 4
+  %.sum100 = add i64 %index, 40
+  %28 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum100
+  %29 = bitcast i32* %28 to <4 x i32>*
+  %wide.load52 = load <4 x i32>* %29, align 4
+  %.sum101 = add i64 %index, 44
+  %30 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum101
+  %31 = bitcast i32* %30 to <4 x i32>*
+  %wide.load53 = load <4 x i32>* %31, align 4
+  %32 = add <4 x i32> zeroinitializer, %vec.phi
+  %33 = add <4 x i32> zeroinitializer, %vec.phi20
+  %34 = add <4 x i32> %wide.load32, %vec.phi21
+  %35 = add <4 x i32> zeroinitializer, %vec.phi23
+  %36 = add <4 x i32> zeroinitializer, %vec.phi24
+  %37 = add <4 x i32> %wide.load36, %vec.phi25
+  %38 = add <4 x i32> %wide.load37, %vec.phi26
+  %39 = add <4 x i32> %wide.load38, %vec.phi27
+  %40 = add <4 x i32> %wide.load39, %vec.phi28
+  %41 = add <4 x i32> %wide.load40, %vec.phi29
+  %42 = add <4 x i32> %wide.load41, %vec.phi30
+  %43 = sub <4 x i32> %32, %wide.load42
+  %44 = sub <4 x i32> %33, %wide.load43
+  %45 = sub <4 x i32> %34, %wide.load44
+  %46 = sub <4 x i32> %35, %wide.load46
+  %47 = sub <4 x i32> %36, %wide.load47
+  %48 = sub <4 x i32> %37, %wide.load48
+  %49 = sub <4 x i32> %38, %wide.load49
+  %50 = sub <4 x i32> %39, %wide.load50
+  %51 = sub <4 x i32> %40, %wide.load51
+  %52 = sub <4 x i32> %41, %wide.load52
+  %53 = sub <4 x i32> %42, %wide.load53
+  %index.next = add i64 %index, 48
+  br i1 false, label %middle.block, label %vector.body
+
+middle.block:                                     ; preds = %vector.body
+  %.lcssa112 = phi <4 x i32> [ %53, %vector.body ]
+  %.lcssa111 = phi <4 x i32> [ %52, %vector.body ]
+  %.lcssa110 = phi <4 x i32> [ %51, %vector.body ]
+  %.lcssa109 = phi <4 x i32> [ %50, %vector.body ]
+  %.lcssa108 = phi <4 x i32> [ %49, %vector.body ]
+  %.lcssa107 = phi <4 x i32> [ %48, %vector.body ]
+  %.lcssa106 = phi <4 x i32> [ %47, %vector.body ]
+  %.lcssa105 = phi <4 x i32> [ %46, %vector.body ]
+  %.lcssa103 = phi <4 x i32> [ %45, %vector.body ]
+  %.lcssa102 = phi <4 x i32> [ %44, %vector.body ]
+  %.lcssa = phi <4 x i32> [ %43, %vector.body ]
+  ret void
+}
+
+attributes #0 = { noinline nounwind }
+

Added: llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy2.ll?rev=229457&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy2.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/vsx-infl-copy2.ll Mon Feb 16 17:46:30 2015
@@ -0,0 +1,115 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc(i32* nocapture readonly %first) #0 {
+entry:
+  br i1 false, label %loop2_start, label %if.end5
+
+; CHECK-LABEL: @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc
+; CHECK: xxlor
+
+loop2_start:                                      ; preds = %loop2_start, %entry
+  br i1 undef, label %loop2_start, label %if.then.i31
+
+if.end5:                                          ; preds = %entry
+  br i1 undef, label %loop_start.preheader, label %if.then.i31
+
+loop_start.preheader:                             ; preds = %if.end5
+  br i1 false, label %middle.block, label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %loop_start.preheader
+  %vec.phi61 = phi <4 x i32> [ %34, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi62 = phi <4 x i32> [ %35, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi63 = phi <4 x i32> [ %36, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi65 = phi <4 x i32> [ %37, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi67 = phi <4 x i32> [ %38, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi68 = phi <4 x i32> [ %39, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi69 = phi <4 x i32> [ %40, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi70 = phi <4 x i32> [ %41, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %vec.phi71 = phi <4 x i32> [ %42, %vector.body ], [ zeroinitializer, %loop_start.preheader ]
+  %.sum = add i64 0, 4
+  %wide.load72 = load <4 x i32>* null, align 4
+  %.sum109 = add i64 0, 8
+  %0 = getelementptr i32* %first, i64 %.sum109
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load73 = load <4 x i32>* %1, align 4
+  %.sum110 = add i64 0, 12
+  %2 = getelementptr i32* %first, i64 %.sum110
+  %3 = bitcast i32* %2 to <4 x i32>*
+  %wide.load74 = load <4 x i32>* %3, align 4
+  %.sum112 = add i64 0, 20
+  %4 = getelementptr i32* %first, i64 %.sum112
+  %5 = bitcast i32* %4 to <4 x i32>*
+  %wide.load76 = load <4 x i32>* %5, align 4
+  %.sum114 = add i64 0, 28
+  %6 = getelementptr i32* %first, i64 %.sum114
+  %7 = bitcast i32* %6 to <4 x i32>*
+  %wide.load78 = load <4 x i32>* %7, align 4
+  %.sum115 = add i64 0, 32
+  %8 = getelementptr i32* %first, i64 %.sum115
+  %9 = bitcast i32* %8 to <4 x i32>*
+  %wide.load79 = load <4 x i32>* %9, align 4
+  %.sum116 = add i64 0, 36
+  %10 = getelementptr i32* %first, i64 %.sum116
+  %11 = bitcast i32* %10 to <4 x i32>*
+  %wide.load80 = load <4 x i32>* %11, align 4
+  %.sum117 = add i64 0, 40
+  %12 = getelementptr i32* %first, i64 %.sum117
+  %13 = bitcast i32* %12 to <4 x i32>*
+  %wide.load81 = load <4 x i32>* %13, align 4
+  %.sum118 = add i64 0, 44
+  %14 = getelementptr i32* %first, i64 %.sum118
+  %15 = bitcast i32* %14 to <4 x i32>*
+  %wide.load82 = load <4 x i32>* %15, align 4
+  %16 = mul <4 x i32> %wide.load72, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %17 = mul <4 x i32> %wide.load73, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %18 = mul <4 x i32> %wide.load74, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %19 = mul <4 x i32> %wide.load76, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %20 = mul <4 x i32> %wide.load78, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %21 = mul <4 x i32> %wide.load79, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %22 = mul <4 x i32> %wide.load80, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %23 = mul <4 x i32> %wide.load81, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %24 = mul <4 x i32> %wide.load82, <i32 269850533, i32 269850533, i32 269850533, i32 269850533>
+  %25 = add <4 x i32> %16, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %26 = add <4 x i32> %17, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %27 = add <4 x i32> %18, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %28 = add <4 x i32> %19, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %29 = add <4 x i32> %20, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %30 = add <4 x i32> %21, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %31 = add <4 x i32> %22, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %32 = add <4 x i32> %23, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %33 = add <4 x i32> %24, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064>
+  %34 = add nsw <4 x i32> %25, %vec.phi61
+  %35 = add nsw <4 x i32> %26, %vec.phi62
+  %36 = add nsw <4 x i32> %27, %vec.phi63
+  %37 = add nsw <4 x i32> %28, %vec.phi65
+  %38 = add nsw <4 x i32> %29, %vec.phi67
+  %39 = add nsw <4 x i32> %30, %vec.phi68
+  %40 = add nsw <4 x i32> %31, %vec.phi69
+  %41 = add nsw <4 x i32> %32, %vec.phi70
+  %42 = add nsw <4 x i32> %33, %vec.phi71
+  br i1 false, label %middle.block, label %vector.body
+
+middle.block:                                     ; preds = %vector.body, %loop_start.preheader
+  %rdx.vec.exit.phi85 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %34, %vector.body ]
+  %rdx.vec.exit.phi86 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %35, %vector.body ]
+  %rdx.vec.exit.phi87 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %36, %vector.body ]
+  %rdx.vec.exit.phi89 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %37, %vector.body ]
+  %rdx.vec.exit.phi91 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %38, %vector.body ]
+  %rdx.vec.exit.phi92 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %39, %vector.body ]
+  %rdx.vec.exit.phi93 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %40, %vector.body ]
+  %rdx.vec.exit.phi94 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %41, %vector.body ]
+  %rdx.vec.exit.phi95 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %42, %vector.body ]
+  br i1 false, label %if.then.i31, label %loop_start.prol
+
+loop_start.prol:                                  ; preds = %loop_start.prol, %middle.block
+  br label %loop_start.prol
+
+if.then.i31:                                      ; preds = %middle.block, %if.end5, %loop2_start
+  unreachable
+}
+
+attributes #0 = { nounwind }
+





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