[PATCH] Code Generator Patterns for X86 Gather and Scatter

[Elena Demikhovsky]

Hi anemet, craig.topper,

This is the second patch for masked gather and scatter intrinsics.
Gather and scatter instructions modify one of the source operands. These instructions zero the mask register.

VGATHERDPS zmm1 {k1}, vm32z
k1[MAX_KL-1:KL] <- 0

Gather instruction actually has 2 destination operands. In order to build a pattern for this instruction, I added a property "hasTwoExplicitDefs" and made some minor changes in the TableGen.

(I commented out some code to make the patch simple for review.)

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D7665

Files:
  ../include/llvm/CodeGen/ISDOpcodes.h
  ../include/llvm/Target/Target.td
  ../include/llvm/Target/TargetSelectionDAG.td
  ../lib/Target/X86/X86InstrAVX512.td
  ../lib/Target/X86/X86InstrFragmentsSIMD.td
  ../lib/Target/X86/X86InstrInfo.td
  ../utils/TableGen/CodeGenDAGPatterns.cpp
  ../utils/TableGen/CodeGenInstruction.cpp
  ../utils/TableGen/CodeGenInstruction.h

EMAIL PREFERENCES
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