[llvm] r229223 - R600/SI: Fix size of VReg_1

[Matt Arsenault]

Author: arsenm
Date: Fri Feb 13 20:51:44 2015
New Revision: 229223

URL: http://llvm.org/viewvc/llvm-project?rev=229223&view=rev
Log:
R600/SI: Fix size of VReg_1

This is really a 32-bit register, if we try to check the size of it,
we want 32-bits.

Modified:
    llvm/trunk/lib/Target/R600/SIRegisterInfo.td

Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.td?rev=229223&r1=229222&r2=229223&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.td Fri Feb 13 20:51:44 2015
@@ -209,7 +209,7 @@ def VReg_256 : RegisterClass<"AMDGPU", [
 
 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
 
-def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>;
+def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>;
 
 class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
   let OperandNamespace = "AMDGPU";