[PATCH] CodeGenPrepare: Avoid and/or i1 in select conditions.

[Ahmed Bougacha]

I should note that this would have been useful as a DAGCombine as
well, because for instance on X86, (select (fcmp oeq/une)) is lowered
into the pattern matched here.

Matthias tells me doing it as a DAGCombine was frowned upon (why?), so
I'm doing pretty much the same thing on X86ISD::CMOV nodes, and will
submit shortly.
-Ahmed


On Fri, Feb 13, 2015 at 1:34 PM, Matthias Braun <matze at braunis.de> wrote:
> Submit again (last time the patch/phabricator version got mixed up...):
>
> This transforms
> select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y)
> select(N0|N1, X, Y) => select(N0, X, select(N1, X, Y))
> for targets where performing and/or on i1 results implies using an
> integer register for a compare result.
>
> REPOSITORY
>   rL LLVM
>
> http://reviews.llvm.org/D7622
>
> Files:
>   include/llvm/Target/TargetLowering.h
>   lib/CodeGen/CodeGenPrepare.cpp
>   lib/Target/PowerPC/PPCISelLowering.h
>   test/CodeGen/R600/or.ll
>   test/CodeGen/X86/jump_sign.ll
>   test/CodeGen/X86/zext-sext.ll
>   test/Transforms/CodeGenPrepare/AArch64/select_and_or.ll
>   test/Transforms/CodeGenPrepare/PowerPC/lit.local.cfg
>   test/Transforms/CodeGenPrepare/PowerPC/select_and_or.ll
>   test/Transforms/CodeGenPrepare/X86/select_and_or.ll
>
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