[PATCH] R600/SI: Misc fixes for special division instructions

[Tom Stellard]

On Tue, Feb 03, 2015 at 08:27:42PM -0800, Matt Arsenault wrote:
> From c2a165818457162c3053284b425f64578e1e1202 Mon Sep 17 00:00:00 2001
> From: Matt Arsenault <Matthew.Arsenault at amd.com>
> Date: Tue, 3 Feb 2015 14:27:18 -0800
> Subject: [PATCH 6/9] R600/SI: Rename encoding field to match docs
> 
> ---
>  lib/Target/R600/SIInstrFormats.td | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
> index 913a769..10683a0 100644
> --- a/lib/Target/R600/SIInstrFormats.td
> +++ b/lib/Target/R600/SIInstrFormats.td
> @@ -337,7 +337,7 @@ class VOP3e <bits<9> op> : Enc64 {
>  
>  class VOP3be <bits<9> op> : Enc64 {
>  
> -  bits<8> dst;
> +  bits<8> vdst;

If you change this, you will also need to change all the operand names
for VOP3 instructions from dst->vdst or else encoding may break.

-Tom

>    bits<2> src0_modifiers;
>    bits<9> src0;
>    bits<2> src1_modifiers;
> @@ -347,7 +347,7 @@ class VOP3be <bits<9> op> : Enc64 {
>    bits<7> sdst;
>    bits<2> omod;
>  
> -  let Inst{7-0} = dst;
> +  let Inst{7-0} = vdst;
>    let Inst{14-8} = sdst;
>    let Inst{25-17} = op;
>    let Inst{31-26} = 0x34; //encoding
> -- 
> 2.2.1
>