[PATCH] [mips] Avoid redundant sign extension of the result of binary bitwise instructions.

[Vasileios Kalintiris]

Hi dsanders,

http://reviews.llvm.org/D7581

Files:
  lib/Target/Mips/Mips64InstrInfo.td
  test/CodeGen/Mips/llvm-ir/and.ll
  test/CodeGen/Mips/llvm-ir/or.ll
  test/CodeGen/Mips/llvm-ir/xor.ll

Index: lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips64InstrInfo.td
+++ lib/Target/Mips/Mips64InstrInfo.td
@@ -486,6 +486,14 @@
 def : MipsPat<(i32 (trunc GPR64:$src)),
               (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
 
+// bypass trunc nodes for bitwise ops
+def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
+              (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
+
 // 32-to-64-bit extension
 def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
 def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
Index: test/CodeGen/Mips/llvm-ir/and.ll
===================================================================
--- test/CodeGen/Mips/llvm-ir/and.ll
+++ test/CodeGen/Mips/llvm-ir/and.ll
@@ -51,10 +51,7 @@
 entry:
 ; ALL-LABEL: and_i32:
 
-  ; GP32:         and     $2, $4, $5
-
-  ; GP64:         and     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          and     $2, $4, $5
 
   %r = and i32 %a, %b
   ret i32 %r
Index: test/CodeGen/Mips/llvm-ir/or.ll
===================================================================
--- test/CodeGen/Mips/llvm-ir/or.ll
+++ test/CodeGen/Mips/llvm-ir/or.ll
@@ -51,11 +51,7 @@
 entry:
 ; ALL-LABEL: or_i32:
 
-  ; GP32:         or     $2, $4, $5
-
-  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
-  ; FIXME: The sll instruction below is redundant.
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          or     $2, $4, $5
 
   %r = or i32 %a, %b
   ret i32 %r
Index: test/CodeGen/Mips/llvm-ir/xor.ll
===================================================================
--- test/CodeGen/Mips/llvm-ir/xor.ll
+++ test/CodeGen/Mips/llvm-ir/xor.ll
@@ -51,10 +51,7 @@
 entry:
 ; ALL-LABEL: xor_i32:
 
-  ; GP32:         xor     $2, $4, $5
-
-  ; GP64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; GP64:         sll     $2, $[[T0]], 0
+  ; ALL:          xor     $2, $4, $5
 
   %r = xor i32 %a, %b
   ret i32 %r

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