[PATCH] Break dependencies in large loops containing reductions (LoopVectorize)

[Olivier Sallenave]

> There is a separate register-pressure heuristic, and already uses a different TTI interface to get the number of available registers. Look at the calculateRegisterUsage() function.


Right, but then why not setting 12 as the max interleave factor for POWER7/POWER8? From our previous discussion (http://reviews.llvm.org/D7503), I understood that you didn't want to put 12 because of potential spillings. I feel like register pressure and available ILP should be completely separated concerns.

> Maybe, but even if we only care about latency combined with ILP, we sometimes are only about ILP independent of latency. Thus, I think having interfaces that return (average) instruction latency, (average) ILP, and whether or not the processor can speculate future loop iterations without dependencies (true for OoO, false for in-order, generically) etc. is the most straightforward from the backend modeling perspective.


This sound great, I would be happy to implement that. I feel like when you talk about ILP, you're talking about number of functional units, am I right? I will try to put something together without changing too much the current policy.

Thanks


http://reviews.llvm.org/D7514

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