[PATCH] [PowerPC] Implement miscellaneous vector logical operations introduced in POWER8

[Kit Barton]

Hi hfinkel, wschmidt, seurer, nemanjai,

This change implements the following three logical vector operations: 
  - veqv (vector equivalence)
  - vnand
  - vorc

I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions.

http://reviews.llvm.org/D7469

Files:
  lib/Target/PowerPC/PPCInstrAltivec.td
  test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
  test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
  test/MC/PowerPC/ppc64-encoding-vmx.s

Index: lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- lib/Target/PowerPC/PPCInstrAltivec.td
+++ lib/Target/PowerPC/PPCInstrAltivec.td
@@ -968,4 +968,20 @@
 def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
                         "vpopcntd $vD, $vB", IIC_VecGeneral,
                         [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
+
+let isCommutable = 1 in {
+let AddedComplexity = 500 in {
+// FIXME: Use AddedComplexity > 400 to ensure these patterns match before the VSX equivalents. We need to fix this up at some point. 
+def VEQV  : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                     "veqv $vD, $vA, $vB", IIC_VecGeneral,
+                     [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
+def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                     "vnand $vD, $vA, $vB", IIC_VecGeneral,
+                     [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
+def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                      "vorc $vD, $vA, $vB", IIC_VecGeneral,
+                      [(set v4i32:$vD, (or v4i32:$vA,
+                                           (vnot_ppc v4i32:$vB)))]>;
+} // AddedComplexity = 500
+} // isCommutable
 } // end HasP8Altivec
Index: test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
===================================================================
--- test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
+++ test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll
@@ -0,0 +1,27 @@
+; Check the miscellaneous logical vector operations added in P8
+; 
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
+; Test x eqv y
+define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: veqv 2, 2, 3
+}
+
+; Test x vnand y
+define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = and <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: vnand 2, 2, 3
+}
+
+; Test x vorc y
+define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
+       %ret_val = or <4 x i32> %x, %tmp
+       ret <4 x i32> %ret_val
+; CHECK: vorc 2, 2, 3      
+}
Index: test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
===================================================================
--- test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -378,6 +378,15 @@
 # CHECK: vandc 2, 3, 4                   
 0x10 0x43 0x24 0x44
 
+# CHECK: veqv 2, 3, 4
+0x10 0x43 0x26 0x84
+
+# CHECK: vnand 2, 3, 4
+0x10 0x43 0x25 0x84
+
+# CHECK: vorc 2, 3, 4
+0x10 0x43 0x25 0x44
+
 # CHECK: vnor 2, 3, 4                    
 0x10 0x43 0x25 0x04
 
Index: test/MC/PowerPC/ppc64-encoding-vmx.s
===================================================================
--- test/MC/PowerPC/ppc64-encoding-vmx.s
+++ test/MC/PowerPC/ppc64-encoding-vmx.s
@@ -408,6 +408,15 @@
 # CHECK-BE: vandc 2, 3, 4                   # encoding: [0x10,0x43,0x24,0x44]
 # CHECK-LE: vandc 2, 3, 4                   # encoding: [0x44,0x24,0x43,0x10]
             vandc 2, 3, 4
+# CHECK-BE: veqv 2, 3, 4                    # encoding: [0x10,0x43,0x26,0x84]
+# CHECK-LE: veqv 2, 3, 4                    # encoding: [0x84,0x26,0x43,0x10]
+            veqv 2, 3, 4
+# CHECK-BE: vnand 2, 3, 4                   # encoding: [0x10,0x43,0x25,0x84]
+# CHECK-LE: vnand 2, 3, 4                   # encoding: [0x84,0x25,0x43,0x10]
+            vnand 2, 3, 4
+# CHECK-BE: vorc 2, 3, 4                    # encoding: [0x10,0x43,0x25,0x44]
+# CHECK-LE: vorc 2, 3, 4                    # encoding: [0x44,0x25,0x43,0x10]
+            vorc 2, 3, 4
 # CHECK-BE: vnor 2, 3, 4                    # encoding: [0x10,0x43,0x25,0x04]
 # CHECK-LE: vnor 2, 3, 4                    # encoding: [0x04,0x25,0x43,0x10]
             vnor 2, 3, 4

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