[llvm] r228349 - [Hexagon] Renaming v4 compare-and-jump instructions.
Colin LeMahieu
colinl at codeaurora.org
Thu Feb 5 14:03:32 PST 2015
Author: colinl
Date: Thu Feb 5 16:03:32 2015
New Revision: 228349
URL: http://llvm.org/viewvc/llvm-project?rev=228349&view=rev
Log:
[Hexagon] Renaming v4 compare-and-jump instructions.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td?rev=228349&r1=228348&r2=228349&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV3.td Thu Feb 5 16:03:32 2015
@@ -83,7 +83,6 @@ let isCodeGenOnly = 1, Defs = VolatileV3
def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
}
-
//===----------------------------------------------------------------------===//
// JR -
//===----------------------------------------------------------------------===//
@@ -92,7 +91,6 @@ let isCodeGenOnly = 1, Defs = VolatileV3
// ALU64/ALU +
//===----------------------------------------------------------------------===//
-
let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23,
validSubTargets = HasV3SubT in
def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=228349&r1=228348&r2=228349&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Thu Feb 5 16:03:32 2015
@@ -1502,7 +1502,7 @@ class NVJrr_template<string mnemonic, bi
let RegOp = !if(!eq(NvOpNum, 0), src2, src1);
let IClass = 0b0010;
- let Inst{26} = 0b0;
+ let Inst{27-26} = 0b00;
let Inst{25-23} = majOp;
let Inst{22} = isNegCond;
let Inst{18-16} = Ns;
@@ -1516,9 +1516,9 @@ class NVJrr_template<string mnemonic, bi
multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum,
bit isNegCond> {
// Branch not taken:
- def _nt_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
+ def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>;
// Branch taken:
- def _t_V4: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
+ def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>;
}
// NvOpNum = 0 -> First Operand is a new-value Register
@@ -1527,8 +1527,8 @@ multiclass NVJrr_cond<string mnemonic, b
multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp,
bit NvOpNum> {
let BaseOpcode = BaseOp#_NVJ in {
- defm _t_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
- defm _f_Jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
+ defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond
+ defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond
}
}
@@ -1540,11 +1540,11 @@ multiclass NVJrr_base<string mnemonic, s
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
- defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
- defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
- defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
- defm CMPLTrr : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
- defm CMPLTUrr : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
+ defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
+ defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
+ defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
+ defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel;
+ defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel;
}
//===----------------------------------------------------------------------===//
@@ -1582,15 +1582,15 @@ class NVJri_template<string mnemonic, bi
multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> {
// Branch not taken:
- def _nt_V4: NVJri_template<mnemonic, majOp, isNegCond, 0>;
+ def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>;
// Branch taken:
- def _t_V4: NVJri_template<mnemonic, majOp, isNegCond, 1>;
+ def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>;
}
multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> {
let BaseOpcode = BaseOp#_NVJri in {
- defm _t_Jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
- defm _f_Jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
+ defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond
+ defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond
}
}
@@ -1600,9 +1600,9 @@ multiclass NVJri_base<string mnemonic, s
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
- defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
- defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
- defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
+ defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
+ defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
+ defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
}
//===----------------------------------------------------------------------===//
@@ -1639,16 +1639,16 @@ class NVJ_ConstImm_template<string mnemo
multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal,
bit isNegCond> {
// Branch not taken:
- def _nt_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
+ def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>;
// Branch taken:
- def _t_V4: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
+ def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>;
}
multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp,
string ImmVal> {
let BaseOpcode = BaseOp#_NVJ_ConstImm in {
- defm _t_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
- defm _f_Jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
+ defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True
+ defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False
}
}
@@ -1658,9 +1658,9 @@ multiclass NVJ_ConstImm_base<string mnem
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
Defs = [PC], hasSideEffects = 0 in {
- defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
- defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
- defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
+ defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
+ defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
+ defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
}
// J4_hintjumpr: Hint indirect conditional jump.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp?rev=228349&r1=228348&r2=228349&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp Thu Feb 5 16:03:32 2015
@@ -299,48 +299,48 @@ static unsigned getNewValueJumpOpcode(Ma
switch (MI->getOpcode()) {
case Hexagon::C2_cmpeq:
- return taken ? Hexagon::CMPEQrr_t_Jumpnv_t_V4
- : Hexagon::CMPEQrr_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpeq_t_jumpnv_t
+ : Hexagon::J4_cmpeq_t_jumpnv_nt;
case Hexagon::C2_cmpeqi: {
if (reg >= 0)
- return taken ? Hexagon::CMPEQri_t_Jumpnv_t_V4
- : Hexagon::CMPEQri_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t
+ : Hexagon::J4_cmpeqi_t_jumpnv_nt;
else
- return taken ? Hexagon::CMPEQn1_t_Jumpnv_t_V4
- : Hexagon::CMPEQn1_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpeqn1_t_jumpnv_t
+ : Hexagon::J4_cmpeqn1_t_jumpnv_nt;
}
case Hexagon::C2_cmpgt: {
if (secondRegNewified)
- return taken ? Hexagon::CMPLTrr_t_Jumpnv_t_V4
- : Hexagon::CMPLTrr_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmplt_t_jumpnv_t
+ : Hexagon::J4_cmplt_t_jumpnv_nt;
else
- return taken ? Hexagon::CMPGTrr_t_Jumpnv_t_V4
- : Hexagon::CMPGTrr_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpgt_t_jumpnv_t
+ : Hexagon::J4_cmpgt_t_jumpnv_nt;
}
case Hexagon::C2_cmpgti: {
if (reg >= 0)
- return taken ? Hexagon::CMPGTri_t_Jumpnv_t_V4
- : Hexagon::CMPGTri_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpgti_t_jumpnv_t
+ : Hexagon::J4_cmpgti_t_jumpnv_nt;
else
- return taken ? Hexagon::CMPGTn1_t_Jumpnv_t_V4
- : Hexagon::CMPGTn1_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpgtn1_t_jumpnv_t
+ : Hexagon::J4_cmpgtn1_t_jumpnv_nt;
}
case Hexagon::C2_cmpgtu: {
if (secondRegNewified)
- return taken ? Hexagon::CMPLTUrr_t_Jumpnv_t_V4
- : Hexagon::CMPLTUrr_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpltu_t_jumpnv_t
+ : Hexagon::J4_cmpltu_t_jumpnv_nt;
else
- return taken ? Hexagon::CMPGTUrr_t_Jumpnv_t_V4
- : Hexagon::CMPGTUrr_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpgtu_t_jumpnv_t
+ : Hexagon::J4_cmpgtu_t_jumpnv_nt;
}
case Hexagon::C2_cmpgtui:
- return taken ? Hexagon::CMPGTUri_t_Jumpnv_t_V4
- : Hexagon::CMPGTUri_t_Jumpnv_nt_V4;
+ return taken ? Hexagon::J4_cmpgtui_t_jumpnv_t
+ : Hexagon::J4_cmpgtui_t_jumpnv_nt;
default:
llvm_unreachable("Could not find matching New Value Jump instruction.");
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