[llvm] r228259 - [ARM] Use patterns instead of hardcoded regs in test. NFC.

[Ahmed Bougacha]

Author: ab
Date: Wed Feb  4 19:52:19 2015
New Revision: 228259

URL: http://llvm.org/viewvc/llvm-project?rev=228259&view=rev
Log:
[ARM] Use patterns instead of hardcoded regs in test.  NFC.

Modified:
    llvm/trunk/test/CodeGen/ARM/big-endian-neon-extend.ll

Modified: llvm/trunk/test/CodeGen/ARM/big-endian-neon-extend.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/big-endian-neon-extend.ll?rev=228259&r1=228258&r2=228259&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/big-endian-neon-extend.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/big-endian-neon-extend.ll Wed Feb  4 19:52:19 2015
@@ -12,7 +12,7 @@ define void @vector_ext_2i8_to_2i64( <2
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
 ; CHECK-NEXT: vand      [[QREG]], [[QREG]], [[MASK]]
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64   {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i8>* %loadaddr
   %2 = zext <2 x i8> %1 to <2 x i64>
@@ -31,7 +31,7 @@ define void @vector_ext_2i16_to_2i64( <2
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
 ; CHECK-NEXT: vand      [[QREG]], [[QREG]], [[MASK]]
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64   {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i16>* %loadaddr
   %2 = zext <2 x i16> %1 to <2 x i64>
@@ -76,8 +76,8 @@ define void @vector_ext_2i8_to_2i16( <2
 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
-; CHECK-NEXT: vuzp.16   [[REG]], d17
-; CHECK-NEXT: vrev32.16 [[REG]], d17
+; CHECK-NEXT: vuzp.16   [[REG]], {{d[0-9]+}}
+; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
 ; CHECK-NEXT: vst1.32   {[[REG]][0]}, [r1:32]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i8>* %loadaddr
@@ -93,7 +93,7 @@ define void @vector_ext_4i8_to_4i32( <4
 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
 ; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64   {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <4 x i8>* %loadaddr
   %2 = zext <4 x i8> %1 to <4 x i32>