[llvm] r228190 - R600/SI: Expand misaligned 16-bit memory accesses
Tom Stellard
thomas.stellard at amd.com
Wed Feb 4 12:49:53 PST 2015
Author: tstellar
Date: Wed Feb 4 14:49:52 2015
New Revision: 228190
URL: http://llvm.org/viewvc/llvm-project?rev=228190&view=rev
Log:
R600/SI: Expand misaligned 16-bit memory accesses
Modified:
llvm/trunk/lib/Target/R600/SIISelLowering.cpp
llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=228190&r1=228189&r2=228190&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Wed Feb 4 14:49:52 2015
@@ -324,6 +324,11 @@ bool SITargetLowering::allowsMisalignedM
return Align % 4 == 0;
}
+ // Smaller than dword value must be aligned.
+ // FIXME: This should be allowed on CI+
+ if (VT.bitsLT(MVT::i32))
+ return false;
+
// 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
// byte-address are ignored, thus forcing Dword alignment.
// This applies to private, global, and constant memory.
Modified: llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll?rev=228190&r1=228189&r2=228190&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll (original)
+++ llvm/trunk/test/CodeGen/R600/unaligned-load-store.ll Wed Feb 4 14:49:52 2015
@@ -1,6 +1,30 @@
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
+; SI-LABEL: {{^}}unaligned_load_store_i16_local:
+; SI: ds_read_u8
+; SI: ds_read_u8
+; SI: ds_write_b8
+; SI: ds_write_b8
+; SI: s_endpgm
+define void @unaligned_load_store_i16_local(i16 addrspace(3)* %p, i16 addrspace(3)* %r) nounwind {
+ %v = load i16 addrspace(3)* %p, align 1
+ store i16 %v, i16 addrspace(3)* %r, align 1
+ ret void
+}
+
+; SI-LABEL: {{^}}unaligned_load_store_i16_global:
+; SI: buffer_load_ubyte
+; SI: buffer_load_ubyte
+; SI: buffer_store_byte
+; SI: buffer_store_byte
+; SI: s_endpgm
+define void @unaligned_load_store_i16_global(i16 addrspace(1)* %p, i16 addrspace(1)* %r) nounwind {
+ %v = load i16 addrspace(1)* %p, align 1
+ store i16 %v, i16 addrspace(1)* %r, align 1
+ ret void
+}
+
; SI-LABEL: {{^}}unaligned_load_store_i32_local:
; SI: ds_read_u8
; SI: ds_read_u8
More information about the llvm-commits
mailing list