[llvm] r228168 - Fixes a bug in vector load legalization that confused bits and bytes.

[Michael Kuperstein]

Author: mkuper
Date: Wed Feb  4 12:54:01 2015
New Revision: 228168

URL: http://llvm.org/viewvc/llvm-project?rev=228168&view=rev
Log:
Fixes a bug in vector load legalization that confused bits and bytes.

Differential Revision: http://reviews.llvm.org/D7400

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    llvm/trunk/test/CodeGen/X86/pr15267.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=228168&r1=228167&r2=228168&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Wed Feb  4 12:54:01 2015
@@ -554,9 +554,9 @@ SDValue VectorLegalizer::ExpandLoad(SDVa
       BitOffset += SrcEltBits;
       if (BitOffset >= WideBits) {
         WideIdx++;
-        Offset -= WideBits;
-        if (Offset > 0) {
-          ShAmt = DAG.getConstant(SrcEltBits - Offset,
+        BitOffset -= WideBits;
+        if (BitOffset > 0) {
+          ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
                                   TLI.getShiftAmountTy(WideVT));
           Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
           Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);

Modified: llvm/trunk/test/CodeGen/X86/pr15267.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr15267.ll?rev=228168&r1=228167&r2=228168&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr15267.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr15267.ll Wed Feb  4 12:54:01 2015
@@ -4,8 +4,7 @@ define <4 x i3> @test1(<4 x i3>* %in) no
   %ret = load <4 x i3>* %in, align 1
   ret <4 x i3> %ret
 }
-
-; CHECK: test1
+; CHECK-LABEL: test1
 ; CHECK: movzwl
 ; CHECK: shrl $3
 ; CHECK: andl $7
@@ -25,7 +24,7 @@ define <4 x i1> @test2(<4 x i1>* %in) no
   ret <4 x i1> %ret
 }
 
-; CHECK: test2
+; CHECK-LABEL: test2
 ; CHECK: movzbl
 ; CHECK: shrl
 ; CHECK: andl $1
@@ -46,7 +45,7 @@ define <4 x i64> @test3(<4 x i1>* %in) n
   ret <4 x i64> %sext
 }
 
-; CHECK: test3
+; CHECK-LABEL: test3
 ; CHECK: movzbl
 ; CHECK: movq
 ; CHECK: shlq
@@ -67,3 +66,71 @@ define <4 x i64> @test3(<4 x i1>* %in) n
 ; CHECK: vpunpcklqdq
 ; CHECK: vinsertf128
 ; CHECK: ret
+
+define <16 x i4> @test4(<16 x i4>* %in) nounwind {
+  %ret = load <16 x i4>* %in, align 1
+  ret <16 x i4> %ret
+}
+
+; CHECK-LABEL: test4
+; CHECK: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: movl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vmovd
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movl
+; CHECK-NEXT: shrl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: movq
+; CHECK-NEXT: shrq
+; CHECK-NEXT: andl
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: shrq
+; CHECK-NEXT: vpinsrb
+; CHECK-NEXT: retq