[llvm] r228140 - Adding support to LLVM for targeting Cortex-A72
Renato Golin
renato.golin at linaro.org
Wed Feb 4 05:31:30 PST 2015
Author: rengolin
Date: Wed Feb 4 07:31:29 2015
New Revision: 228140
URL: http://llvm.org/viewvc/llvm-project?rev=228140&view=rev
Log:
Adding support to LLVM for targeting Cortex-A72
Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp
load balancing pass isn't enabled for Cortex-A72 as it's not
profitable to have it enabled for this core.
Patch by Ranjeet Singh.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/ARM/ARM.td
llvm/trunk/test/CodeGen/AArch64/cpus.ll
llvm/trunk/test/CodeGen/AArch64/remat.ll
llvm/trunk/test/CodeGen/ARM/build-attributes.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=228140&r1=228139&r2=228140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Wed Feb 4 07:31:29 2015
@@ -91,6 +91,8 @@ def : ProcessorModel<"generic", NoSchedM
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
+// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
+def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=228140&r1=228139&r2=228140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Wed Feb 4 07:31:29 2015
@@ -416,6 +416,10 @@ def : ProcNoItin<"cortex-a53", [Pro
def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass,
FeatureDB, FeatureFPARMv8,
FeatureNEON, FeatureDSPThumb2]>;
+// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
+def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass,
+ FeatureDB, FeatureFPARMv8,
+ FeatureNEON, FeatureDSPThumb2]>;
// Cyclone is very similar to swift
def : ProcessorModel<"cyclone", SwiftModel,
Modified: llvm/trunk/test/CodeGen/AArch64/cpus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cpus.ll?rev=228140&r1=228139&r2=228140&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/cpus.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/cpus.ll Wed Feb 4 07:31:29 2015
@@ -4,6 +4,7 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID
; CHECK-NOT: {{.*}} is not a recognized processor for this target
Modified: llvm/trunk/test/CodeGen/AArch64/remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/remat.ll?rev=228140&r1=228139&r2=228140&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/remat.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/remat.ll Wed Feb 4 07:31:29 2015
@@ -1,5 +1,6 @@
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
%X = type { i64, i64, i64 }
declare void @f(%X*)
Modified: llvm/trunk/test/CodeGen/ARM/build-attributes.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/build-attributes.ll?rev=228140&r1=228139&r2=228140&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/build-attributes.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/build-attributes.ll Wed Feb 4 07:31:29 2015
@@ -76,6 +76,9 @@
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-CHECK-FAST
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-NOFPU
@@ -96,6 +99,9 @@
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
+; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; ARMv7a
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
@@ -938,6 +944,36 @@
; CORTEX-A57-FAST-NOT: .eabi_attribute 22
; CORTEX-A57-FAST: .eabi_attribute 23, 1
+; CORTEX-A72: .cpu cortex-a72
+; CORTEX-A72: .eabi_attribute 6, 14
+; CORTEX-A72: .eabi_attribute 7, 65
+; CORTEX-A72: .eabi_attribute 8, 1
+; CORTEX-A72: .eabi_attribute 9, 2
+; CORTEX-A72: .fpu crypto-neon-fp-armv8
+; CORTEX-A72: .eabi_attribute 12, 3
+; CORTEX-A72-NOT: .eabi_attribute 19
+;; We default to IEEE 754 compliance
+; CORTEX-A72: .eabi_attribute 20, 1
+; CORTEX-A72: .eabi_attribute 21, 1
+; CORTEX-A72-NOT: .eabi_attribute 22
+; CORTEX-A72: .eabi_attribute 23, 3
+; CORTEX-A72: .eabi_attribute 24, 1
+; CORTEX-A72: .eabi_attribute 25, 1
+; CORTEX-A72-NOT: .eabi_attribute 27
+; CORTEX-A72-NOT: .eabi_attribute 28
+; CORTEX-A72: .eabi_attribute 36, 1
+; CORTEX-A72: .eabi_attribute 38, 1
+; CORTEX-A72: .eabi_attribute 42, 1
+; CORTEX-A72-NOT: .eabi_attribute 44
+; CORTEX-A72: .eabi_attribute 68, 3
+
+; CORTEX-A72-FAST-NOT: .eabi_attribute 19
+;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
+; CORTEX-A72-FAST: .eabi_attribute 20, 2
+; CORTEX-A72-FAST-NOT: .eabi_attribute 21
+; CORTEX-A72-FAST-NOT: .eabi_attribute 22
+; CORTEX-A72-FAST: .eabi_attribute 23, 1
+
; RELOC-PIC: .eabi_attribute 15, 1
; RELOC-PIC: .eabi_attribute 16, 1
; RELOC-PIC: .eabi_attribute 17, 2
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