[llvm] r227977 - Revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

[Bill Schmidt]

Author: wschmidt
Date: Tue Feb  3 10:24:05 2015
New Revision: 227977

URL: http://llvm.org/viewvc/llvm-project?rev=227977&view=rev
Log:
Revise too-restrictive test CodeGen/PowerPC/tls-pic.ll

Modified:
    llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll

Modified: llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll?rev=227977&r1=227976&r2=227977&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-pic.ll Tue Feb  3 10:24:05 2015
@@ -19,32 +19,32 @@ entry:
 
 ; OPT0-LABEL: main:
 ; OPT0:      addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
-; OPT0-NEXT: addi 3, [[REG]], a at got@tlsld at l
+; OPT0:      addi 3, [[REG]], a at got@tlsld at l
 ; OPT0:      bl __tls_get_addr(a at tlsld)
 ; OPT0-NEXT: nop
 ; OPT0:      addis [[REG2:[0-9]+]], 3, a at dtprel@ha
-; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a at dtprel@l
+; OPT0:      addi {{[0-9]+}}, [[REG2]], a at dtprel@l
 ; OPT0-32-LABEL: main
 ; OPT0-32:        addi {{[0-9]+}}, {{[0-9]+}}, a at got@tlsld
 ; OPT0-32:        bl __tls_get_addr(a at tlsld)@PLT
 ; OPT0-32:        addis [[REG:[0-9]+]], 3, a at dtprel@ha
-; OPT0-32-NEXT:   addi  {{[0-9]+}}, [[REG]], a at dtprel@l
+; OPT0-32:        addi  {{[0-9]+}}, [[REG]], a at dtprel@l
 ; OPT1-32-LABEL: main
 ; OPT1-32:        addi 3, {{[0-9]+}}, a at got@tlsld
 ; OPT1-32:        bl __tls_get_addr(a at tlsld)@PLT
 ; OPT1-32:        addis [[REG:[0-9]+]], 3, a at dtprel@ha
-; OPT1-32-NEXT:   addi  {{[0-9]+}}, [[REG]], a at dtprel@l
+; OPT1-32:        addi  {{[0-9]+}}, [[REG]], a at dtprel@l
 
 ; Test peephole optimization for thread-local storage using the
 ; local dynamic model.
 
 ; OPT1-LABEL: main:
 ; OPT1:      addis [[REG:[0-9]+]], 2, a at got@tlsld at ha
-; OPT1-NEXT: addi 3, [[REG]], a at got@tlsld at l
+; OPT1:      addi 3, [[REG]], a at got@tlsld at l
 ; OPT1:      bl __tls_get_addr(a at tlsld)
 ; OPT1-NEXT: nop
 ; OPT1:      addis [[REG2:[0-9]+]], 3, a at dtprel@ha
-; OPT1-NEXT: lwa {{[0-9]+}}, a at dtprel@l([[REG2]])
+; OPT1:      lwa {{[0-9]+}}, a at dtprel@l([[REG2]])
 
 ; Test correct assembly code generation for thread-local storage using
 ; the general dynamic model.