[llvm] r227871 - Cache and use the subtarget that owns the target lowering.
Eric Christopher
echristo at gmail.com
Mon Feb 2 14:11:36 PST 2015
Author: echristo
Date: Mon Feb 2 16:11:36 2015
New Revision: 227871
URL: http://llvm.org/viewvc/llvm-project?rev=227871&view=rev
Log:
Cache and use the subtarget that owns the target lowering.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=227871&r1=227870&r2=227871&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Mon Feb 2 16:11:36 2015
@@ -463,8 +463,7 @@ HexagonTargetLowering::LowerCall(TargetL
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;
- const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>(
- DAG.getSubtarget().getRegisterInfo());
+ const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
SDValue StackPtr =
DAG.getCopyFromReg(Chain, dl, QRI->getStackRegister(), getPointerTy());
@@ -722,9 +721,7 @@ SDValue HexagonTargetLowering::LowerINLI
cast<RegisterSDNode>(Node->getOperand(i))->getReg();
// Check it to be lr
- const HexagonRegisterInfo *QRI =
- static_cast<const HexagonRegisterInfo *>(
- DAG.getSubtarget().getRegisterInfo());
+ const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
if (Reg == QRI->getRARegister()) {
FuncInfo->setHasClobberLR(true);
break;
@@ -817,8 +814,7 @@ HexagonTargetLowering::LowerDYNAMIC_STAC
// The Sub result contains the new stack start address, so it
// must be placed in the stack pointer register.
- const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>(
- DAG.getSubtarget().getRegisterInfo());
+ const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
SDValue CopyChain = DAG.getCopyToReg(Chain, dl, QRI->getStackRegister(), Sub);
SDValue Ops[2] = { ArgAdjust, CopyChain };
@@ -965,7 +961,7 @@ HexagonTargetLowering::LowerConstantPool
SDValue
HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
- const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
+ const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
MFI->setReturnAddressIsTaken(true);
@@ -991,8 +987,7 @@ HexagonTargetLowering::LowerRETURNADDR(S
SDValue
HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
- const HexagonRegisterInfo *TRI = static_cast<const HexagonRegisterInfo *>(
- DAG.getSubtarget().getRegisterInfo());
+ const HexagonRegisterInfo *TRI = Subtarget->getRegisterInfo();
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true);
@@ -1044,17 +1039,15 @@ HexagonTargetLowering::LowerBlockAddress
// TargetLowering Implementation
//===----------------------------------------------------------------------===//
-HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &targetmachine)
- : TargetLowering(targetmachine),
- TM(targetmachine) {
-
- const HexagonSubtarget &Subtarget = TM.getSubtarget<HexagonSubtarget>();
+HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
+ const HexagonSubtarget &STI)
+ : TargetLowering(TM), Subtarget(&STI) {
// Set up the register classes.
addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
- if (Subtarget.hasV5TOps()) {
+ if (Subtarget->hasV5TOps()) {
addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
}
@@ -1120,7 +1113,7 @@ HexagonTargetLowering::HexagonTargetLowe
setOperationAction(ISD::FSIN, MVT::f32, Expand);
setOperationAction(ISD::FSIN, MVT::f64, Expand);
- if (Subtarget.hasV5TOps()) {
+ if (Subtarget->hasV5TOps()) {
// Hexagon V5 Support.
setOperationAction(ISD::FADD, MVT::f32, Legal);
setOperationAction(ISD::FADD, MVT::f64, Expand);
@@ -1346,7 +1339,7 @@ HexagonTargetLowering::HexagonTargetLowe
setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
- if (Subtarget.hasV5TOps()) {
+ if (Subtarget->hasV5TOps()) {
// We need to make the operation type of SELECT node to be Custom,
// such that we don't go into the infinite loop of
@@ -1441,7 +1434,7 @@ HexagonTargetLowering::HexagonTargetLowe
setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
- if (Subtarget.isSubtargetV2()) {
+ if (Subtarget->isSubtargetV2()) {
setExceptionPointerRegister(Hexagon::R20);
setExceptionSelectorRegister(Hexagon::R21);
} else {
@@ -1465,8 +1458,7 @@ HexagonTargetLowering::HexagonTargetLowe
setMinFunctionAlignment(2);
// Needed for DYNAMIC_STACKALLOC expansion.
- const HexagonRegisterInfo *QRI = static_cast<const HexagonRegisterInfo *>(
- TM.getSubtargetImpl()->getRegisterInfo());
+ const HexagonRegisterInfo *QRI = Subtarget->getRegisterInfo();
setStackPointerRegisterToSaveRestore(QRI->getStackRegister());
setSchedulingPreference(Sched::VLIW);
}
@@ -1637,7 +1629,7 @@ HexagonTargetLowering::getRegForInlineAs
/// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool.
bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
- return TM.getSubtarget<HexagonSubtarget>().hasV5TOps();
+ return Subtarget->hasV5TOps();
}
/// isLegalAddressingMode - Return true if the addressing mode represented by
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=227871&r1=227870&r2=227871&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Mon Feb 2 16:11:36 2015
@@ -77,6 +77,8 @@ bool isPositiveHalfWord(SDNode *N);
};
}
+ class HexagonSubtarget;
+
class HexagonTargetLowering : public TargetLowering {
int VarArgsFrameOffset; // Frame offset to start of varargs area.
@@ -84,8 +86,9 @@ bool isPositiveHalfWord(SDNode *N);
unsigned& RetSize) const;
public:
- const TargetMachine &TM;
- explicit HexagonTargetLowering(const TargetMachine &targetmachine);
+ const HexagonSubtarget *Subtarget;
+ explicit HexagonTargetLowering(const TargetMachine &TM,
+ const HexagonSubtarget &Subtarget);
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Targets which want to do tail call
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=227871&r1=227870&r2=227871&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Mon Feb 2 16:11:36 2015
@@ -74,7 +74,7 @@ HexagonSubtarget::initializeSubtargetDep
HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU.str()),
- InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM),
+ InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(*TM.getDataLayout()), FrameLowering() {
// Initialize scheduling itinerary for the specified CPU.
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