[llvm] r227832 - Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction

[Eric Christopher]

Author: echristo
Date: Mon Feb  2 12:46:31 2015
New Revision: 227832

URL: http://llvm.org/viewvc/llvm-project?rev=227832&view=rev
Log:
Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction
and remove unnecessary class variables.

Modified:
    llvm/trunk/lib/Target/Hexagon/Hexagon.h
    llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp

Modified: llvm/trunk/lib/Target/Hexagon/Hexagon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Hexagon.h?rev=227832&r1=227831&r2=227832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/Hexagon.h (original)
+++ llvm/trunk/lib/Target/Hexagon/Hexagon.h Mon Feb  2 12:46:31 2015
@@ -39,8 +39,7 @@ namespace llvm {
   FunctionPass *createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM);
   FunctionPass *createHexagonSplitConst32AndConst64(
                       const HexagonTargetMachine &TM);
-  FunctionPass *createHexagonExpandPredSpillCode(
-                      const HexagonTargetMachine &TM);
+  FunctionPass *createHexagonExpandPredSpillCode();
   FunctionPass *createHexagonHardwareLoops();
   FunctionPass *createHexagonPeephole();
   FunctionPass *createHexagonFixupHwLoops();

Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp?rev=227832&r1=227831&r2=227832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp Mon Feb  2 12:46:31 2015
@@ -20,7 +20,6 @@
 #include "Hexagon.h"
 #include "HexagonMachineFunctionInfo.h"
 #include "HexagonSubtarget.h"
-#include "HexagonTargetMachine.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LatencyPriorityQueue.h"
 #include "llvm/CodeGen/MachineDominators.h"
@@ -49,13 +48,9 @@ namespace llvm {
 namespace {
 
 class HexagonExpandPredSpillCode : public MachineFunctionPass {
-    const HexagonTargetMachine& QTM;
-    const HexagonSubtarget &QST;
-
  public:
     static char ID;
-    HexagonExpandPredSpillCode(const HexagonTargetMachine& TM) :
-      MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {
+    HexagonExpandPredSpillCode() : MachineFunctionPass(ID) {
       PassRegistry &Registry = *PassRegistry::getPassRegistry();
       initializeHexagonExpandPredSpillCodePass(Registry);
     }
@@ -72,7 +67,9 @@ char HexagonExpandPredSpillCode::ID = 0;
 
 bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
 
-  const HexagonInstrInfo *TII = QTM.getSubtargetImpl()->getInstrInfo();
+  const HexagonSubtarget &QST = Fn.getSubtarget<HexagonSubtarget>();
+  const HexagonRegisterInfo *TRI = QST.getRegisterInfo();
+  const HexagonInstrInfo *TII = QST.getInstrInfo();
 
   // Loop over all of the basic blocks.
   for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
@@ -86,10 +83,8 @@ bool HexagonExpandPredSpillCode::runOnMa
       if (Opc == Hexagon::STriw_pred) {
         // STriw_pred [R30], ofst, SrcReg;
         unsigned FP = MI->getOperand(0).getReg();
-        assert(
-            FP ==
-                QTM.getSubtargetImpl()->getRegisterInfo()->getFrameRegister() &&
-            "Not a Frame Pointer, Nor a Spill Slot");
+        assert(FP == TRI->getFrameRegister() &&
+               "Not a Frame Pointer, Nor a Spill Slot");
         assert(MI->getOperand(1).isImm() && "Not an offset");
         int Offset = MI->getOperand(1).getImm();
         int SrcReg = MI->getOperand(2).getReg();
@@ -135,10 +130,8 @@ bool HexagonExpandPredSpillCode::runOnMa
         assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
                "Not a predicate register");
         unsigned FP = MI->getOperand(1).getReg();
-        assert(
-            FP ==
-                QTM.getSubtargetImpl()->getRegisterInfo()->getFrameRegister() &&
-            "Not a Frame Pointer, Nor a Spill Slot");
+        assert(FP == TRI->getFrameRegister() &&
+               "Not a Frame Pointer, Nor a Spill Slot");
         assert(MI->getOperand(2).isImm() && "Not an offset");
         int Offset = MI->getOperand(2).getImm();
         if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {
@@ -200,6 +193,6 @@ void llvm::initializeHexagonExpandPredSp
 }
 
 FunctionPass*
-llvm::createHexagonExpandPredSpillCode(const HexagonTargetMachine &TM) {
-  return new HexagonExpandPredSpillCode(TM);
+llvm::createHexagonExpandPredSpillCode() {
+  return new HexagonExpandPredSpillCode();
 }

Modified: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp?rev=227832&r1=227831&r2=227832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp Mon Feb  2 12:46:31 2015
@@ -160,7 +160,7 @@ void HexagonPassConfig::addPreEmitPass()
     addPass(createHexagonNewValueJump(), false);
 
   // Expand Spill code for predicate registers.
-  addPass(createHexagonExpandPredSpillCode(TM), false);
+  addPass(createHexagonExpandPredSpillCode(), false);
 
   // Split up TFRcondsets into conditional transfers.
   addPass(createHexagonSplitTFRCondSets(TM), false);