[PATCH] Fix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0.

[JF Bastien]

lgtm otherwise.


================
Comment at: lib/Target/ARM/ARMBaseInstrInfo.cpp:2570
@@ -2562,1 +2569,3 @@
           }
+          }
+        }
----------------
I think it would be better to rewire the code as:
```
          switch (CC) {
          case ARMCC::EQ: // Z
          case ARMCC::NE: // Z
          case ARMCC::MI: // N
          case ARMCC::PL: // N
          case ARMCC::AL: // none
            // CPSR can be used multiple times, we should continue.
            break;
          case ARMCC::CS: // C
          case ARMCC::CC: // C
          case ARMCC::VS: // V
          case ARMCC::VC: // V
          case ARMCC::HI: // C Z
          case ARMCC::LS: // C Z
          case ARMCC::GE: // N V
          case ARMCC::LT: // N V
          case ARMCC::GT: // Z N V
          case ARMCC::LE: // Z N V
            // The instruction uses the V bit or C bit which is not safe.
            return false;
          }
```

http://reviews.llvm.org/D7274

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