[PATCH] Change more of the guts of CodeGenRegister's RegUnit tracking to be based on bit vectors.

[Chandler Carruth]

Generally looks fine. Feel free to submit whenever. Minor comments and a question below.


REPOSITORY
  rL LLVM

================
Comment at: utils/TableGen/CodeGenRegisters.cpp:202
@@ -213,8 +201,3 @@
 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
-  unsigned OldNumUnits = RegUnits.size();
-
-  SparseBitVector<> NewUnits;
-  for (unsigned RU : RegUnits)
-    NewUnits.set(RU);
-
+  bool changed = false;
   for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
----------------
s/changed/Changed

================
Comment at: utils/TableGen/CodeGenRegisters.cpp:522
@@ -550,3 +521,3 @@
   unsigned Weight = 0;
-  for (RegUnitList::const_iterator I = RegUnits.begin(), E = RegUnits.end();
+  for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
        I != E; ++I) {
----------------
range based loop?

================
Comment at: utils/TableGen/RegisterInfoEmitter.cpp:576
@@ -575,3 +575,3 @@
 static
-DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
+DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) {
   assert(V.empty() && "Clear DiffVec before diffEncode.");
----------------
Why pass by value here? Should this be a const reference?

http://reviews.llvm.org/D7301

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