[llvm] r227613 - [Hexagon] Adding vector predicate instructions.
Colin LeMahieu
colinl at codeaurora.org
Fri Jan 30 13:24:07 PST 2015
Author: colinl
Date: Fri Jan 30 15:24:06 2015
New Revision: 227613
URL: http://llvm.org/viewvc/llvm-project?rev=227613&view=rev
Log:
[Hexagon] Adding vector predicate instructions.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=227613&r1=227612&r2=227613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Fri Jan 30 15:24:06 2015
@@ -991,18 +991,24 @@ class T_vcmp_pat<InstHexagon MI, PatFrag
(i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
// Vector compare bytes
+let isCodeGenOnly = 0 in {
def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
+}
// Vector compare halfwords
+let isCodeGenOnly = 0 in {
def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
+}
// Vector compare words
+let isCodeGenOnly = 0 in {
def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
+}
def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=227613&r1=227612&r2=227613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Fri Jan 30 15:24:06 2015
@@ -2298,6 +2298,65 @@ def M4_pmpyw_acc : T_XTYPE_mpy64_acc <
//===----------------------------------------------------------------------===//
+// ALU64/Vector compare
+//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// Template class for vector compare
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0 in
+class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd>
+ : ALU64_rr <(outs PredRegs:$Pd),
+ (ins DoubleRegs:$Rss, ImmOprnd:$Imm),
+ "$Pd = "#Str#"($Rss, #$Imm)",
+ [], "", ALU64_tc_2early_SLOT23> {
+ bits<2> Pd;
+ bits<5> Rss;
+ bits<32> Imm;
+ bits<8> ImmBits;
+ let ImmBits{6-0} = Imm{6-0};
+ let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu
+
+ let IClass = 0b1101;
+
+ let Inst{27-24} = 0b1100;
+ let Inst{22-21} = cmpOp;
+ let Inst{20-16} = Rss;
+ let Inst{12-5} = ImmBits;
+ let Inst{4-3} = minOp;
+ let Inst{1-0} = Pd;
+ }
+
+// Vector compare bytes
+let isCodeGenOnly = 0 in
+def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>;
+def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
+
+let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
+let isCodeGenOnly = 0 in
+def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
+
+let isCodeGenOnly = 0 in {
+def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
+def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
+def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
+}
+
+// Vector compare halfwords
+let isCodeGenOnly = 0 in {
+def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
+def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
+def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
+}
+
+// Vector compare words
+let isCodeGenOnly = 0 in {
+def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
+def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
+def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
+}
+
+//===----------------------------------------------------------------------===//
// XTYPE/SHIFT +
//===----------------------------------------------------------------------===//
// Shift by immediate and accumulate/logical.
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt?rev=227613&r1=227612&r2=227613&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt Fri Jan 30 15:24:06 2015
@@ -1,9 +1,13 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.10.7 XTYPE/PRED
+# Bounds check
0x83 0xf4 0x10 0xd2
# CHECK: p3 = boundscheck(r17:16, r21:20):raw:lo
0xa3 0xf4 0x10 0xd2
# CHECK: p3 = boundscheck(r17:16, r21:20):raw:hi
+
+# Compare byte
0x43 0xd5 0xd1 0xc7
# CHECK: p3 = cmpb.gt(r17, r21)
0xc3 0xd5 0xd1 0xc7
@@ -16,6 +20,8 @@
# CHECK: p3 = cmpb.gt(r17, #21)
0xa3 0xc2 0x51 0xdd
# CHECK: p3 = cmpb.gtu(r17, #21)
+
+# Compare half
0x63 0xd5 0xd1 0xc7
# CHECK: p3 = cmph.eq(r17, r21)
0x83 0xd5 0xd1 0xc7
@@ -28,12 +34,16 @@
# CHECK: p3 = cmph.gt(r17, #21)
0xab 0xc2 0x51 0xdd
# CHECK: p3 = cmph.gtu(r17, #21)
+
+# Compare doublewords
0x03 0xde 0x94 0xd2
# CHECK: p3 = cmp.eq(r21:20, r31:30)
0x43 0xde 0x94 0xd2
# CHECK: p3 = cmp.gt(r21:20, r31:30)
0x83 0xde 0x94 0xd2
# CHECK: p3 = cmp.gtu(r21:20, r31:30)
+
+# Compare bitmask
0x03 0xd5 0x91 0x85
# CHECK: p3 = bitsclr(r17, #21)
0x03 0xd5 0xb1 0x85
@@ -46,14 +56,22 @@
# CHECK: p3 = bitsclr(r17, r21)
0x03 0xd5 0xb1 0xc7
# CHECK: p3 = !bitsclr(r17, r21)
+
+# mask generate from predicate
0x10 0xc3 0x00 0x86
# CHECK: r17:16 = mask(p3)
+
+# Check for TLB match
0x63 0xf5 0x10 0xd2
# CHECK: p3 = tlbmatch(r17:16, r21)
+
+# Predicate Transfer
0x03 0xc0 0x45 0x85
# CHECK: p3 = r5
0x05 0xc0 0x43 0x89
# CHECK: r5 = p3
+
+# Test bit
0x03 0xd5 0x11 0x85
# CHECK: p3 = tstbit(r17, #21)
0x03 0xd5 0x31 0x85
@@ -62,7 +80,57 @@
# CHECK: p3 = tstbit(r17, r21)
0x03 0xd5 0x31 0xc7
# CHECK: p3 = !tstbit(r17, r21)
+
+# Vector compare halfwords
+0x63 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.eq(r21:20, r31:30)
+0x83 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gt(r21:20, r31:30)
+0xa3 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gtu(r21:20, r31:30)
+0xeb 0xc3 0x14 0xdc
+# CHECK: p3 = vcmph.eq(r21:20, #31)
+0xeb 0xc3 0x34 0xdc
+# CHECK: p3 = vcmph.gt(r21:20, #31)
+0xeb 0xc3 0x54 0xdc
+# CHECK: p3 = vcmph.gtu(r21:20, #31)
+
+# Vector compare bytes for any match
+0x03 0xfe 0x14 0xd2
+# CHECK: p3 = any8(vcmpb.eq(r21:20, r31:30))
+
+# Vector compare bytes
+0x63 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.eq(r21:20, r31:30)
+0x83 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gt(r21:20, r31:30)
+0xa3 0xde 0x14 0xd2
+# CHECK: p3 = vcmph.gtu(r21:20, r31:30)
+0xeb 0xc3 0x14 0xdc
+# CHECK: p3 = vcmph.eq(r21:20, #31)
+0xeb 0xc3 0x34 0xdc
+# CHECK: p3 = vcmph.gt(r21:20, #31)
+0xeb 0xc3 0x54 0xdc
+# CHECK: p3 = vcmph.gtu(r21:20, #31)
+
+# Vector compare words
+0x03 0xde 0x14 0xd2
+# CHECK: p3 = vcmpw.eq(r21:20, r31:30)
+0x23 0xde 0x14 0xd2
+# CHECK: p3 = vcmpw.gt(r21:20, r31:30)
+0x43 0xde 0x14 0xd2
+# CHECK: p3 = vcmpw.gtu(r21:20, r31:30)
+0xf3 0xc3 0x14 0xdc
+# CHECK: p3 = vcmpw.eq(r21:20, #31)
+0xf3 0xc3 0x34 0xdc
+# CHECK: p3 = vcmpw.gt(r21:20, #31)
+0xf3 0xc3 0x54 0xdc
+# CHECK: p3 = vcmpw.gtu(r21:20, #31)
+
+# Viterbi pack even and odd predicate bits
0x11 0xc2 0x03 0x89
# CHECK: r17 = vitpack(p3, p2)
+
+# Vector mux
0x70 0xde 0x14 0xd1
# CHECK: r17:16 = vmux(p3, r21:20, r31:30)
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