[llvm] r227588 - [Hexagon] Adding a number of vector load variants and organizing tests.

Colin LeMahieu colinl at codeaurora.org
Fri Jan 30 10:09:44 PST 2015


Author: colinl
Date: Fri Jan 30 12:09:44 2015
New Revision: 227588

URL: http://llvm.org/viewvc/llvm-project?rev=227588&view=rev
Log:
[Hexagon] Adding a number of vector load variants and organizing tests.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
    llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt
    llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=227588&r1=227587&r2=227588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Fri Jan 30 12:09:44 2015
@@ -1741,6 +1741,16 @@ defm loadri: LD_Idxd <"memw", "LDriw", I
 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
 
+let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
+  def L2_loadbsw2_io:   T_load_io<"membh",  IntRegs, 0b0001, s11_1Ext>;
+  def L2_loadbzw2_io:   T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
+}
+
+let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in {
+  def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
+  def L2_loadbsw4_io: T_load_io<"membh",  DoubleRegs, 0b0111, s11_2Ext>;
+}
+
 // Patterns to select load-indexed (i.e. load from base+offset).
 multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
                      InstHexagon MI> {
@@ -1895,6 +1905,18 @@ defm loadri : LD_PostInc <"memw", "LDriw
 let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
 
+// Rd=memb[u]h(Rx++#s4:1)
+// Rdd=memb[u]h(Rx++#s4:2)
+let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
+  def L2_loadbsw2_pi   : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
+  def L2_loadbzw2_pi   : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
+}
+let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0,
+    isCodeGenOnly = 0 in {
+  def L2_loadbsw4_pi   : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
+  def L2_loadbzw4_pi   : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
+}
+
 //===----------------------------------------------------------------------===//
 // Template class for post increment loads with register offset.
 //===----------------------------------------------------------------------===//
@@ -1927,10 +1949,14 @@ let hasNewValue = 1, isCodeGenOnly = 0 i
   def L2_loadrh_pr  : T_load_pr <"memh",  IntRegs, 0b1010, HalfWordAccess>;
   def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
   def L2_loadri_pr  : T_load_pr <"memw",  IntRegs, 0b1100, WordAccess>;
+
+  def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
 }
 
-let isCodeGenOnly = 0 in
+let isCodeGenOnly = 0 in {
 def L2_loadrd_pr   : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
+def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
+}
 
 // Load predicate.
 let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
@@ -1982,10 +2008,16 @@ let accessSize = ByteAccess, isCodeGenOn
 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
   def L2_loadrh_pcr   : T_load_pcr <"memh",   IntRegs, 0b1010>;
   def L2_loadruh_pcr  : T_load_pcr <"memuh",  IntRegs, 0b1011>;
+  def L2_loadbsw2_pcr : T_load_pcr <"membh",  IntRegs, 0b0001>;
+  def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
 }
 
 let accessSize = WordAccess, isCodeGenOnly = 0 in {
   def  L2_loadri_pcr  : T_load_pcr <"memw", IntRegs, 0b1100>;
+  let hasNewValue = 0 in {
+    def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
+    def L2_loadbsw4_pcr : T_load_pcr <"membh",  DoubleRegs, 0b0111>;
+  }
 }
 
 let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
@@ -2033,12 +2065,19 @@ let accessSize = ByteAccess, isCodeGenOn
 let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
   def L2_loadrh_pci   : T_load_pci <"memh",   IntRegs, s4_1Imm, 0b1010>;
   def L2_loadruh_pci  : T_load_pci <"memuh",  IntRegs, s4_1Imm, 0b1011>;
+  def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
+  def L2_loadbsw2_pci : T_load_pci <"membh",  IntRegs, s4_1Imm, 0b0001>;
 }
 
 // Word variants of circ load
 let accessSize = WordAccess, isCodeGenOnly = 0 in
 def L2_loadri_pci   : T_load_pci <"memw",   IntRegs,    s4_2Imm, 0b1100>;
 
+let accessSize = WordAccess, hasNewValue = 0, isCodeGenOnly = 0 in {
+  def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
+  def L2_loadbsw4_pci : T_load_pci <"membh",  DoubleRegs, s4_2Imm, 0b0111>;
+}
+
 let accessSize = DoubleWordAccess, hasNewValue = 0, isCodeGenOnly = 0 in
 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
 
@@ -2094,11 +2133,16 @@ let hasNewValue =1, opNewValue = 0, isCo
   def L2_loadrub_pbr  : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
   def L2_loadrh_pbr   : T_load_pbr <"memh",  IntRegs, HalfWordAccess, 0b1010>;
   def L2_loadruh_pbr  : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
+  def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
+  def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
   def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
 }
 
-let isCodeGenOnly = 0 in
+let isCodeGenOnly = 0 in {
+def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
+def L2_loadbsw4_pbr : T_load_pbr <"membh",  DoubleRegs, WordAccess, 0b0111>;
 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
+}
 
 //===----------------------------------------------------------------------===//
 // LD -

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=227588&r1=227587&r2=227588&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Fri Jan 30 12:09:44 2015
@@ -335,21 +335,43 @@ def A4_combineii: ALU32Inst<(outs Double
 //===----------------------------------------------------------------------===//
 // Template class for load instructions with Absolute set addressing mode.
 //===----------------------------------------------------------------------===//
-let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
-validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
-class T_LD_abs_set<string mnemonic, RegisterClass RC>:
-            LDInst2<(outs RC:$dst1, IntRegs:$dst2),
-            (ins u0AlwaysExt:$addr),
-            "$dst1 = "#mnemonic#"($dst2=##$addr)",
-            []>,
-            Requires<[HasV4T]>;
+let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
+    hasSideEffects = 0 in
+class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
+            LDInst<(outs RC:$dst1, IntRegs:$dst2),
+            (ins u6Ext:$addr),
+            "$dst1 = "#mnemonic#"($dst2 = #$addr)",
+            []> {
+  bits<7> name;
+  bits<5> dst1;
+  bits<5> dst2;
+  bits<6> addr;
+
+  let IClass = 0b1001;
+  let Inst{27-25} = 0b101;
+  let Inst{24-21} = MajOp;
+  let Inst{13-12} = 0b01;
+  let Inst{4-0}   = dst1;
+  let Inst{20-16} = dst2;
+  let Inst{11-8}  = addr{5-2};
+  let Inst{6-5}   = addr{1-0};
+}
+
+let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
+  def L4_loadrb_ap   : T_LD_abs_set <"memb",   IntRegs, 0b1000>;
+  def L4_loadrub_ap  : T_LD_abs_set <"memub",  IntRegs, 0b1001>;
+}
+
+let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
+  def L4_loadrh_ap  : T_LD_abs_set <"memh",  IntRegs, 0b1010>;
+  def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
+}
 
-def LDrid_abs_set_V4  : T_LD_abs_set <"memd", DoubleRegs>;
-def LDrib_abs_set_V4  : T_LD_abs_set <"memb", IntRegs>;
-def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
-def LDrih_abs_set_V4  : T_LD_abs_set <"memh", IntRegs>;
-def LDriw_abs_set_V4  : T_LD_abs_set <"memw", IntRegs>;
-def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
+let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
+  def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
+
+let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
+def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
 
 //===----------------------------------------------------------------------===//
 // Template classes for the non-predicated load instructions with
@@ -1200,6 +1222,16 @@ let addrMode = BaseImmOffset, InputType
 }
 
 //===----------------------------------------------------------------------===//
+// Post increment loads with register offset.
+//===----------------------------------------------------------------------===//
+
+let hasNewValue = 1, isCodeGenOnly = 0 in
+def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
+
+let isCodeGenOnly = 0 in
+def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
+
+//===----------------------------------------------------------------------===//
 // Template class for non-predicated post increment .new stores
 // mem[bhwd](Rx++#s4:[0123])=Nt.new
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt?rev=227588&r1=227587&r2=227588&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/jr.txt Fri Jan 30 12:09:44 2015
@@ -1,11 +1,19 @@
 # RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.3 JR
 
+# Call subroutine from register
 0x00 0xc0 0xb5 0x50
 # CHECK: callr r21
 0x00 0xc1 0x15 0x51
 # CHECK: if (p1) callr r21
 0x00 0xc3 0x35 0x51
 # CHECK: if (!p3) callr r21
+
+# Hint an indirect jump address
+0x00 0xc0 0xb5 0x52
+# CHECK: hintjr(r21)
+
+# Jump to address from register
 0x00 0xc0 0x95 0x52
 # CHECK: jumpr r21
 0x00 0xc1 0x55 0x53

Modified: llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=227588&r1=227587&r2=227588&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt Fri Jan 30 12:09:44 2015
@@ -1,5 +1,7 @@
-# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
+# Hexagon Programmer's Reference Manual 11.5 LD
 
+# Load doubleword
 0x90 0xff 0xd5 0x3a
 # CHECK: r17:16 = memd(r21 + r31<<#3)
 0x10 0xc5 0xc0 0x49
@@ -14,6 +16,8 @@
 # CHECK: r17:16 = memd(r21++m1)
 0x10 0xe0 0xd5 0x9f
 # CHECK: r17:16 = memd(r21 ++ m1:brev)
+
+# Load doubleword conditionally
 0xf0 0xff 0xd5 0x30
 # CHECK: if (p3) r17:16 = memd(r21+r31<<#3)
 0xf0 0xff 0xd5 0x31
@@ -45,6 +49,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17:16 = memd(r21++#40)
 
+# Load byte
 0x91 0xff 0x15 0x3a
 # CHECK: r17 = memb(r21 + r31<<#3)
 0xb1 0xc2 0x00 0x49
@@ -61,6 +66,8 @@
 # CHECK: r17 = memb(r21++m1)
 0x11 0xe0 0x15 0x9f
 # CHECK: r17 = memb(r21 ++ m1:brev)
+
+# Load byte conditionally
 0xf1 0xff 0x15 0x30
 # CHECK: if (p3) r17 = memb(r21+r31<<#3)
 0xf1 0xff 0x15 0x31
@@ -92,6 +99,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
 
+# Load halfword
 0x91 0xff 0x55 0x3a
 # CHECK: r17 = memh(r21 + r31<<#3)
 0x51 0xc5 0x40 0x49
@@ -108,6 +116,8 @@
 # CHECK: r17 = memh(r21++m1)
 0x11 0xe0 0x55 0x9f
 # CHECK: r17 = memh(r21 ++ m1:brev)
+
+# Load halfword conditionally
 0xf1 0xff 0x55 0x30
 # CHECK: if (p3) r17 = memh(r21+r31<<#3)
 0xf1 0xff 0x55 0x31
@@ -129,6 +139,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10)
 
+# Load unsigned byte
 0x91 0xff 0x35 0x3a
 # CHECK: r17 = memub(r21 + r31<<#3)
 0xb1 0xc2 0x20 0x49
@@ -145,6 +156,8 @@
 # CHECK: r17 = memub(r21++m1)
 0x11 0xe0 0x35 0x9f
 # CHECK: r17 = memub(r21 ++ m1:brev)
+
+# Load unsigned byte conditionally
 0xf1 0xff 0x35 0x30
 # CHECK: if (p3) r17 = memub(r21+r31<<#3)
 0xf1 0xff 0x35 0x31
@@ -176,6 +189,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5)
 
+# Load unsigned halfword
 0x91 0xff 0x75 0x3a
 # CHECK: r17 = memuh(r21 + r31<<#3)
 0x51 0xc5 0x60 0x49
@@ -192,6 +206,8 @@
 # CHECK: r17 = memuh(r21++m1)
 0x11 0xe0 0x75 0x9f
 # CHECK: r17 = memuh(r21 ++ m1:brev)
+
+# Load unsigned halfword conditionally
 0xf1 0xff 0x75 0x30
 # CHECK: if (p3) r17 = memuh(r21+r31<<#3)
 0xf1 0xff 0x75 0x31
@@ -223,6 +239,7 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memuh(r21++#10)
 
+# Load word
 0x91 0xff 0x95 0x3a
 # CHECK: r17 = memw(r21 + r31<<#3)
 0x91 0xc2 0x80 0x49
@@ -239,6 +256,8 @@
 # CHECK: r17 = memw(r21++m1)
 0x11 0xe0 0x95 0x9f
 # CHECK: r17 = memw(r21 ++ m1:brev)
+
+# Load word conditionally
 0xf1 0xff 0x95 0x30
 # CHECK: if (p3) r17 = memw(r21+r31<<#3)
 0xf1 0xff 0x95 0x31
@@ -270,8 +289,11 @@
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) r17 = memw(r21++#20)
 
+# Deallocate stack frame
 0x1e 0xc0 0x1e 0x90
 # CHECK: deallocframe
+
+# Deallocate stack frame and return
 0x1e 0xc0 0x1e 0x96
 # CHECK: dealloc_return
 0x03 0x40 0x45 0x85 0x1e 0xcb 0x1e 0x96
@@ -290,3 +312,53 @@
 0x03 0x40 0x45 0x85 0x1e 0xfb 0x1e 0x96
 # CHECK: p3 = r5
 # CHECK-NEXT: if (!p3.new) dealloc_return:t
+
+# Load and unpack bytes to halfwords
+0xf1 0xc3 0x35 0x90
+# CHECK: r17 = membh(r21 + #62)
+0xf1 0xc3 0x75 0x90
+# CHECK: r17 = memubh(r21 + #62)
+0xf0 0xc3 0xb5 0x90
+# CHECK: r17:16 = memubh(r21 + #124)
+0xf0 0xc3 0xf5 0x90
+# CHECK: r17:16 = membh(r21 + #124)
+0xb1 0xe0 0x35 0x98
+# CHECK: r17 = membh(r21 ++ #10:circ(m1))
+0x11 0xe2 0x35 0x98
+# CHECK: r17 = membh(r21 ++ I:circ(m1))
+0xb1 0xe0 0x75 0x98
+# CHECK: r17 = memubh(r21 ++ #10:circ(m1))
+0x11 0xe2 0x75 0x98
+# CHECK: r17 = memubh(r21 ++ I:circ(m1))
+0xb0 0xe0 0xf5 0x98
+# CHECK: r17:16 = membh(r21 ++ #20:circ(m1))
+0x10 0xe2 0xf5 0x98
+# CHECK: r17:16 = membh(r21 ++ I:circ(m1))
+0xb0 0xe0 0xb5 0x98
+# CHECK: r17:16 = memubh(r21 ++ #20:circ(m1))
+0x10 0xe2 0xb5 0x98
+# CHECK: r17:16 = memubh(r21 ++ I:circ(m1))
+0xb1 0xc0 0x35 0x9a
+# CHECK: r17 = membh(r21++#10)
+0xb1 0xc0 0x75 0x9a
+# CHECK: r17 = memubh(r21++#10)
+0xb0 0xc0 0xb5 0x9a
+# CHECK: r17:16 = memubh(r21++#20)
+0xb0 0xc0 0xf5 0x9a
+# CHECK: r17:16 = membh(r21++#20)
+0x11 0xe0 0x35 0x9c
+# CHECK: r17 = membh(r21++m1)
+0x11 0xe0 0x75 0x9c
+# CHECK: r17 = memubh(r21++m1)
+0x10 0xe0 0xf5 0x9c
+# CHECK: r17:16 = membh(r21++m1)
+0x10 0xe0 0xb5 0x9c
+# CHECK: r17:16 = memubh(r21++m1)
+0x11 0xe0 0x35 0x9e
+# CHECK: r17 = membh(r21 ++ m1:brev)
+0x11 0xe0 0x75 0x9e
+# CHECK: r17 = memubh(r21 ++ m1:brev)
+0x10 0xe0 0xb5 0x9e
+# CHECK: r17:16 = memubh(r21 ++ m1:brev)
+0x10 0xe0 0xf5 0x9e
+# CHECK: r17:16 = membh(r21 ++ m1:brev)





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