[llvm] r227474 - [Hexagon] Deleting old variants of intrinsics and adding missing tests.
Colin LeMahieu
colinl at codeaurora.org
Thu Jan 29 09:26:56 PST 2015
Author: colinl
Date: Thu Jan 29 11:26:56 2015
New Revision: 227474
URL: http://llvm.org/viewvc/llvm-project?rev=227474&view=rev
Log:
[Hexagon] Deleting old variants of intrinsics and adding missing tests.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV5.td
llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll
llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td?rev=227474&r1=227473&r2=227474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td Thu Jan 29 11:26:56 2015
@@ -597,6 +597,38 @@ def : T_R_pat<A2_zxth, int_hexagon_A2_zx
def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
/********************************************************************
+* ALU32/PRED *
+*********************************************************************/
+// Compare
+def : T_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>;
+def : T_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>;
+def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
+
+def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
+def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
+def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
+
+def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
+ (i32 (C2_cmpgti (I32:$src1),
+ (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
+
+def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
+ (i32 (C2_cmpgtui (I32:$src1),
+ (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
+
+// The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
+def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
+ (i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>;
+
+def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1),
+ (I32:$src2))),
+ (i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>;
+
+def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1),
+ (I32:$src2))),
+ (i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>;
+
+/********************************************************************
* ALU64/ALU *
*********************************************************************/
def: T_RR_pat<A2_addsat, int_hexagon_A2_addsat>;
@@ -608,6 +640,10 @@ def: T_PP_pat<A2_andp, int_hexagon_A
def: T_PP_pat<A2_orp, int_hexagon_A2_orp>;
def: T_PP_pat<A2_xorp, int_hexagon_A2_xorp>;
+def: T_PP_pat<C2_cmpeqp, int_hexagon_C2_cmpeqp>;
+def: T_PP_pat<C2_cmpgtp, int_hexagon_C2_cmpgtp>;
+def: T_PP_pat<C2_cmpgtup, int_hexagon_C2_cmpgtup>;
+
def: T_PP_pat<S2_parityp, int_hexagon_S2_parityp>;
def: T_RR_pat<S2_packhl, int_hexagon_S2_packhl>;
@@ -622,6 +658,27 @@ def : T_PRR_pat <M2_dpmpyss_nac_s0, int_
def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
+/********************************************************************
+* CR *
+*********************************************************************/
+class qi_CRInst_qi_pat<InstHexagon Inst, Intrinsic IntID> :
+ Pat<(i32 (IntID IntRegs:$Rs)),
+ (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>;
+
+class qi_CRInst_qiqi_pat<InstHexagon Inst, Intrinsic IntID> :
+ Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)),
+ (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>;
+
+def: qi_CRInst_qi_pat<C2_not, int_hexagon_C2_not>;
+def: qi_CRInst_qi_pat<C2_all8, int_hexagon_C2_all8>;
+def: qi_CRInst_qi_pat<C2_any8, int_hexagon_C2_any8>;
+
+def: qi_CRInst_qiqi_pat<C2_and, int_hexagon_C2_and>;
+def: qi_CRInst_qiqi_pat<C2_andn, int_hexagon_C2_andn>;
+def: qi_CRInst_qiqi_pat<C2_or, int_hexagon_C2_or>;
+def: qi_CRInst_qiqi_pat<C2_orn, int_hexagon_C2_orn>;
+def: qi_CRInst_qiqi_pat<C2_xor, int_hexagon_C2_xor>;
+
// Multiply 32x32 and use lower result
def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
@@ -1331,40 +1388,6 @@ class di_LDInstPI_diu4<string opc, Intri
"$src1 = $dst">;
/********************************************************************
-* ALU32/PERM *
-*********************************************************************/
-
-// ALU32 / PERM / Mux.
-def HEXAGON_C2_mux:
- si_ALU32_qisisi <"mux", int_hexagon_C2_mux>;
-
-/********************************************************************
-* ALU32/PRED *
-*********************************************************************/
-
-// ALU32 / PRED / Compare.
-def HEXAGON_C2_cmpeq:
- qi_ALU32_sisi <"cmp.eq", int_hexagon_C2_cmpeq>;
-def HEXAGON_C2_cmpeqi:
- qi_ALU32_sis10 <"cmp.eq", int_hexagon_C2_cmpeqi>;
-def HEXAGON_C2_cmpgei:
- qi_ALU32_sis8 <"cmp.ge", int_hexagon_C2_cmpgei>;
-def HEXAGON_C2_cmpgeui:
- qi_ALU32_siu8 <"cmp.geu", int_hexagon_C2_cmpgeui>;
-def HEXAGON_C2_cmpgt:
- qi_ALU32_sisi <"cmp.gt", int_hexagon_C2_cmpgt>;
-def HEXAGON_C2_cmpgti:
- qi_ALU32_sis10 <"cmp.gt", int_hexagon_C2_cmpgti>;
-def HEXAGON_C2_cmpgtu:
- qi_ALU32_sisi <"cmp.gtu", int_hexagon_C2_cmpgtu>;
-def HEXAGON_C2_cmpgtui:
- qi_ALU32_siu9 <"cmp.gtu", int_hexagon_C2_cmpgtui>;
-def HEXAGON_C2_cmplt:
- qi_ALU32_sisi <"cmp.lt", int_hexagon_C2_cmplt>;
-def HEXAGON_C2_cmpltu:
- qi_ALU32_sisi <"cmp.ltu", int_hexagon_C2_cmpltu>;
-
-/********************************************************************
* ALU32/VH *
*********************************************************************/
@@ -1393,18 +1416,6 @@ def HEXAGON_A2_svsubhs:
def HEXAGON_A2_svsubuhs:
si_ALU32_sisi_sat <"vsubuh", int_hexagon_A2_svsubuhs>;
-/********************************************************************
-* ALU64/ALU *
-*********************************************************************/
-
-// ALU64 / ALU / Compare.
-def HEXAGON_C2_cmpeqp:
- qi_ALU64_didi <"cmp.eq", int_hexagon_C2_cmpeqp>;
-def HEXAGON_C2_cmpgtp:
- qi_ALU64_didi <"cmp.gt", int_hexagon_C2_cmpgtp>;
-def HEXAGON_C2_cmpgtup:
- qi_ALU64_didi <"cmp.gtu", int_hexagon_C2_cmpgtup>;
-
// ALU64 / ALU / Transfer register.
def HEXAGON_A2_tfrp:
di_ALU64_di <"", int_hexagon_A2_tfrp>;
@@ -1564,34 +1575,6 @@ def HEXAGON_A2_vsubw:
def HEXAGON_A2_vsubws:
di_ALU64_didi_sat <"vsubw", int_hexagon_A2_vsubws>;
-
-/********************************************************************
-* CR *
-*********************************************************************/
-
-// CR / Logical reductions on predicates.
-def HEXAGON_C2_all8:
- qi_SInst_qi <"all8", int_hexagon_C2_all8>;
-def HEXAGON_C2_any8:
- qi_SInst_qi <"any8", int_hexagon_C2_any8>;
-
-// CR / Logical operations on predicates.
-def HEXAGON_C2_pxfer_map:
- qi_SInst_qi_pxfer <"", int_hexagon_C2_pxfer_map>;
-def HEXAGON_C2_and:
- qi_SInst_qiqi <"and", int_hexagon_C2_and>;
-def HEXAGON_C2_andn:
- qi_SInst_qiqi_neg <"and", int_hexagon_C2_andn>;
-def HEXAGON_C2_not:
- qi_SInst_qi <"not", int_hexagon_C2_not>;
-def HEXAGON_C2_or:
- qi_SInst_qiqi <"or", int_hexagon_C2_or>;
-def HEXAGON_C2_orn:
- qi_SInst_qiqi_neg <"or", int_hexagon_C2_orn>;
-def HEXAGON_C2_xor:
- qi_SInst_qiqi <"xor", int_hexagon_C2_xor>;
-
-
/********************************************************************
* MTYPE/ALU *
*********************************************************************/
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td?rev=227474&r1=227473&r2=227474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td Thu Jan 29 11:26:56 2015
@@ -206,103 +206,3 @@ def : T_RI_pat <A4_round_ri_sat, int_hex
def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
-
-class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
- : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
- !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
-
-class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
- : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
- !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
-
-class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
- : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
- !strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
-
-//
-// SInst Classes.
-//
-class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
- : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
- !strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
-
-class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
- : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3),
- !strconcat("$dst = ", !strconcat(opc ,
- "($src1, and($src2, !$src3)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3))]>;
-
-class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
- : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3),
- !strconcat("$dst = ", !strconcat(opc ,
- "($src1, and($src2, $src3)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3))]>;
-
-class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
- : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3),
- !strconcat("$dst = ", !strconcat(opc ,
- "($src1, or($src2, !$src3)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3))]>;
-
-class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
- : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3),
- !strconcat("$dst = ", !strconcat(opc ,
- "($src1, or($src2, $src3)")),
- [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
- IntRegs:$src3))]>;
-
-/********************************************************************
-* ALU32/PRED *
-*********************************************************************/
-
-// ALU32 / PRED / Conditional Shift Halfword.
-// ALU32 / PRED / Conditional Sign Extend.
-// ALU32 / PRED / Conditional Zero Extend.
-// ALU32 / PRED / Compare.
-def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
-def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
-def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
-
-def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
-def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
-def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
-
-
-/********************************************************************
-* CR *
-*********************************************************************/
-
-// CR / Corner Detection Acceleration.
-def Hexagon_C4_fastcorner9:
- qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
-def Hexagon_C4_fastcorner9_not:
- qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
-
-// CR / Logical Operations On Predicates.
-def Hexagon_C4_and_andn:
- qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
-def Hexagon_C4_and_and:
- qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
-def Hexagon_C4_and_orn:
- qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
-def Hexagon_C4_and_or:
- qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
-def Hexagon_C4_or_andn:
- qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
-def Hexagon_C4_or_and:
- qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
-def Hexagon_C4_or_orn:
- qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
-def Hexagon_C4_or_or:
- qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV5.td?rev=227474&r1=227473&r2=227474&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV5.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV5.td Thu Jan 29 11:26:56 2015
@@ -17,6 +17,9 @@ def : T_FF_pat<F2_sffixupn, int_hexagon_
def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>;
def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>;
+def: qi_CRInst_qiqi_pat<C4_fastcorner9, int_hexagon_C4_fastcorner9>;
+def: qi_CRInst_qiqi_pat<C4_fastcorner9_not, int_hexagon_C4_fastcorner9_not>;
+
def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>;
def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>;
@@ -104,10 +107,6 @@ class di_MInst_diu4_rnd<string opc, Intr
!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
-def HEXAGON_C4_fastcorner9:
- qi_SInst_qiqi <"fastcorner9", int_hexagon_C4_fastcorner9>;
-def HEXAGON_C4_fastcorner9_not:
- qi_SInst_qiqi <"!fastcorner9", int_hexagon_C4_fastcorner9_not>;
def HEXAGON_M5_vrmpybuu:
di_MInst_didi <"vrmpybu", int_hexagon_M5_vrmpybuu>;
def HEXAGON_M5_vrmacbuu:
@@ -132,11 +131,3 @@ def HEXAGON_A5_vaddhubs:
si_SInst_didi_sat <"vaddhub", int_hexagon_A5_vaddhubs>;
def HEXAGON_S5_vasrhrnd_goodsyntax:
di_MInst_diu4_rnd <"vasrh", int_hexagon_S5_vasrhrnd_goodsyntax>;
-def HEXAGON_F2_sfcmpeq:
- qi_SInst_sfsf <"sfcmp.eq", int_hexagon_F2_sfcmpeq>;
-def HEXAGON_F2_sfcmpgt:
- qi_SInst_sfsf <"sfcmp.gt", int_hexagon_F2_sfcmpgt>;
-def HEXAGON_F2_sfcmpge:
- qi_SInst_sfsf <"sfcmp.ge", int_hexagon_F2_sfcmpge>;
-def HEXAGON_F2_sfcmpuo:
- qi_SInst_sfsf <"sfcmp.uo", int_hexagon_F2_sfcmpuo>;
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll?rev=227474&r1=227473&r2=227474&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/alu32_perm.ll Thu Jan 29 11:26:56 2015
@@ -2,6 +2,20 @@
; Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
; Combine words into doubleword
+declare i64 @llvm.hexagon.A4.combineri(i32, i32)
+define i64 @A4_combineri(i32 %a) {
+ %z = call i64 @llvm.hexagon.A4.combineri(i32 %a, i32 0)
+ ret i64 %z
+}
+; CHECK: = combine(r0, #0)
+
+declare i64 @llvm.hexagon.A4.combineir(i32, i32)
+define i64 @A4_combineir(i32 %a) {
+ %z = call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %a)
+ ret i64 %z
+}
+; CHECK: = combine(#0, r0)
+
declare i64 @llvm.hexagon.A2.combineii(i32, i32)
define i64 @A2_combineii() {
%z = call i64 @llvm.hexagon.A2.combineii(i32 0, i32 0)
@@ -59,6 +73,13 @@ define i32 @C2_muxir(i32 %a, i32 %b) {
}
; CHECK: r0 = mux(p0, r1, #0)
+declare i32 @llvm.hexagon.C2.mux(i32, i32, i32)
+define i32 @C2_mux(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 @llvm.hexagon.C2.mux(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: r0 = mux(p0, r1, r2)
+
; Shift word by 16
declare i32 @llvm.hexagon.A2.aslh(i32)
define i32 @A2_aslh(i32 %a) {
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll?rev=227474&r1=227473&r2=227474&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/cr.ll Thu Jan 29 11:26:56 2015
@@ -7,14 +7,14 @@ define i32 @C4_fastcorner9(i32 %a, i32 %
%z = call i32 at llvm.hexagon.C4.fastcorner9(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: p0 = fastcorner9(r0, r1)
+; CHECK: p0 = fastcorner9(p0, p1)
declare i32 @llvm.hexagon.C4.fastcorner9.not(i32, i32)
define i32 @C4_fastcorner9_not(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C4.fastcorner9.not(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: p0 = !fastcorner9(r0, r1)
+; CHECK: p0 = !fastcorner9(p0, p1)
; Logical reductions on predicates
declare i32 @llvm.hexagon.C2.any8(i32)
@@ -22,7 +22,7 @@ define i32 @C2_any8(i32 %a) {
%z = call i32 at llvm.hexagon.C2.any8(i32 %a)
ret i32 %z
}
-; CHECK: p0 = any8(r0)
+; CHECK: p0 = any8(p0)
declare i32 @llvm.hexagon.C2.all8(i32)
define i32 @C2_all8(i32 %a) {
@@ -30,7 +30,7 @@ define i32 @C2_all8(i32 %a) {
ret i32 %z
}
-; CHECK: p0 = all8(r0)
+; CHECK: p0 = all8(p0)
; Logical operations on predicates
declare i32 @llvm.hexagon.C2.and(i32, i32)
@@ -38,39 +38,95 @@ define i32 @C2_and(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.and(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: p0 = and(r0, r1)
+; CHECK: p0 = and(p0, p1)
+
+declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32)
+define i32 @C4_and_and(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.and.and(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = and(p0, and(p1, p2))
declare i32 @llvm.hexagon.C2.or(i32, i32)
define i32 @C2_or(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.or(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: p0 = or(r0, r1)
+; CHECK: p0 = or(p0, p1)
+
+declare i32 @llvm.hexagon.C4.and.or(i32, i32, i32)
+define i32 @C4_and_or(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.and.or(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = and(p0, or(p1, p2))
declare i32 @llvm.hexagon.C2.xor(i32, i32)
define i32 @C2_xor(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.xor(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: p0 = xor(r0, r1)
+; CHECK: p0 = xor(p0, p1)
+
+declare i32 @llvm.hexagon.C4.or.and(i32, i32, i32)
+define i32 @C4_or_and(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.or.and(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = or(p0, and(p1, p2))
declare i32 @llvm.hexagon.C2.andn(i32, i32)
define i32 @C2_andn(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.andn(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: p0 = and(r0, !r1)
+; CHECK: p0 = and(p0, !p1)
+
+declare i32 @llvm.hexagon.C4.or.or(i32, i32, i32)
+define i32 @C4_or_or(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.or.or(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = or(p0, or(p1, p2))
+
+declare i32 @llvm.hexagon.C4.and.andn(i32, i32, i32)
+define i32 @C4_and_andn(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.and.andn(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = and(p0, and(p1, !p2))
+
+declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
+define i32 @C4_and_orn(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = and(p0, or(p1, !p2))
declare i32 @llvm.hexagon.C2.not(i32)
define i32 @C2_not(i32 %a) {
%z = call i32 at llvm.hexagon.C2.not(i32 %a)
ret i32 %z
}
-; CHECK: p0 = not(r0)
+; CHECK: p0 = not(p0)
+
+declare i32 @llvm.hexagon.C4.or.andn(i32, i32, i32)
+define i32 @C4_or_andn(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.or.andn(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = or(p0, and(p1, !p2))
declare i32 @llvm.hexagon.C2.orn(i32, i32)
define i32 @C2_orn(i32 %a, i32 %b) {
%z = call i32 at llvm.hexagon.C2.orn(i32 %a, i32 %b)
ret i32 %z
}
-; CHECK: p0 = or(r0, !r1)
+; CHECK: p0 = or(p0, !p1)
+
+declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
+define i32 @C4_or_orn(i32 %a, i32 %b, i32 %c) {
+ %z = call i32 at llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
+ ret i32 %z
+}
+; CHECK: p0 = or(p0, or(p1, !p2))
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll?rev=227474&r1=227473&r2=227474&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_alu.ll Thu Jan 29 11:26:56 2015
@@ -543,3 +543,11 @@ define i32 @A2_subh_h16_sat_hh(i32 %a, i
ret i32 %z
}
; CHECK: r0 = sub(r0.h, r1.h):sat:<<16
+
+; Sign extend word to doubleword
+declare i64 @llvm.hexagon.A2.sxtw(i32)
+define i64 @A2_sxtw(i32 %a) {
+ %z = call i64 @llvm.hexagon.A2.sxtw(i32 %a)
+ ret i64 %z
+}
+; CHECK: = sxtw(r0)
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