[PATCH] [X86][SSE] Added general integer shuffle matching for MOVQ instruction

[Simon Pilgrim]

Hi chandlerc, andreadb, spatel, qcolombet,

This patch adds general shuffle pattern matching for the MOVQ zero-extend instruction (copy lower 64bits, zero upper) for all 128-bit integer vectors, it is added as a fallback test in lowerVectorShuffleAsZeroOrAnyExtend.

Regarding the issues in the tests - combine-or.ll is fixed in conjunction with D6649 (which reduces it to a shift + movq) and the superfluous movq after the pshufb in vector-shuffle-128-v16.ll are resolved once x86-experimental-vector-shuffle-legality is enabled.

This is a follow-up to D7228 which adds shuffle decodes / assembly comments for the movq comments - if that ticket gets approved I can update this patch's tests to include the comments.

Note I have other patterns to add to lowerVectorShuffleAsZeroOrAnyExtend shortly.

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D7256

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-or.ll
  test/CodeGen/X86/vector-shuffle-128-v16.ll

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