[llvm] r227311 - Correct the AggressiveAntiDepBreaker's handling of subregisters defining super registers
Hal Finkel
hfinkel at anl.gov
Wed Jan 28 06:44:15 PST 2015
Author: hfinkel
Date: Wed Jan 28 08:44:14 2015
New Revision: 227311
URL: http://llvm.org/viewvc/llvm-project?rev=227311&view=rev
Log:
Correct the AggressiveAntiDepBreaker's handling of subregisters defining super registers
As the AggressiveAntiDepBreaker iterated backward through a scheduling region,
we must leave super registers live through subregister definitions so that all
relevant subregister definitions are renamed together. The problem was that we
were also discarding sub-register use locations as the sub-registers are
redefined. The result is that we'd rename the super register along with some,
but not all, subregister definitions.
R0_D = {R0_L, R1_L}
R0_L = {R0_S, R1_S}
%R0_L<def> = TRLi9 16, pred:8, pred:%noreg
%R1_L<def> = LSRLrr %R1_L<kill>, %R0_S, pred:8, pred:%noreg
%R0_L<def> = LSRLrr %R2_L, %R0_S, pred:8, pred:%noreg, %R0_L<imp-use,kill>
%R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg
%R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg
%R4_D<def> = ASRDrr %R0_D<kill>, %R6_S
Anti: %R4_D<def> = ASRDrr %R0_D<kill>, %R6_S
Def Groups: R4_D=g213->g215(via R4_S)->g214(via R4_L)->g216(via R5_S)->g216(via R4_L)->g217(via R5_L)
Use Groups: R0_D=g0->g218(last-use) R1_L->g219(last-use) R6_S=g204->g220(last-use)
Anti: %R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg
Def Groups: R0_L=g208->g209(via R0_S)->g218(via R0_D)->g210(via R1_S)->g210(via R0_D)
Antidep reg: R0_L (real dependency)
Use Groups: R0_L=g210->g224(last-use) R0_S->g225(last-use) R1_S->g226(last-use)
Anti: %R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg
Def Groups: R1_L=g219->g210(via R0_D)
Antidep reg: R1_L (real dependency)
Use Groups: R1_L=g210->g229(last-use)
Anti: %R0_L<def> = LSRLrr %R2_L, %R0_S, pred:8, pred:%noreg, %R0_L<imp-use,kill>
Def Groups: R0_L=g224->g225(via R0_S)->g210(via R0_D)->g226(via R1_S)->g226(via R0_D)
Antidep reg: R0_L Use Groups: R2_L=g192 R0_S=g226->g230(last-use) R0_L=g226->g231(last-use) R1_S->g232(last-use)
Anti: %R1_L<def> = LSRLrr %R1_L<kill>, %R0_S, pred:8, pred:%noreg
Def Groups: R1_L=g229->g226(via R0_D)
Antidep reg: R1_L Use Groups: R1_L=g226->g233(last-use) R0_S=g230
Anti: %R0_L<def> = TRLi9 16, pred:8, pred:%noreg
Def Groups: R0_L=g231->g230(via R0_S)->g226(via R0_D)->g232(via R1_S)->g232(via R0_D)
Antidep reg: R0_L
Rename Candidates for Group g232:
R0_D: elcInt64Regs :: R0_D R1_D R2_D R3_D R4_D R5_D R8_D R9_D R10_D R11_D R12_D R13_D R14_D R15_D R16_D R17_D R18_D R19_D R20_D R21_D R22_D R23_D R24_D R25_D
R0_L: elcIntRegs :: R0_L R1_L R2_L R3_L R4_L R5_L R8_L R9_L R10_L R11_L R12_L R13_L R14_L R15_L R16_L R17_L R18_L R19_L R20_L R21_L R22_L R23_L R24_L R25_L
R0_S: elcShrtRegs elcShrtRegs :: R0_S R1_S R2_S R3_S R4_S R5_S R8_S R9_S R10_S R11_S R12_S R13_S R14_S R15_S R16_S R17_S R18_S R19_S R20_S R21_S R22_S R23_S R24_S R25_S
Find Registers: [R12_D: R12_D R12_L R12_S]
Breaking anti-dependence edge on R0_L: R0_D->R12_D(1 refs) R0_L->R12_L(2 refs) R0_S->R12_S(2 refs)
Use Groups:
...
%R12_L<def> = TRLi9 16, pred:8, pred:%noreg
%R1_L<def> = LSRLrr %R1_L<kill>, %R12_S, pred:8, pred:%noreg
%R0_L<def> = LSRLrr %R2_L<kill>, %R12_S, pred:8, pred:%noreg, %R12_L<imp-use>
%R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg
%R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg
%R4_D<def> = ASRDrr %R12_D<kill>, %R6_S
With this change, we now produce:
Anti: %R4_D<def> = ASRDrr %R0_D<kill>, %R6_S
Def Groups: R4_D=g213->g215(via R4_S)->g214(via R4_L)->g216(via R5_S)->g216(via R4_L)->g217(via R5_L)
Use Groups: R0_D=g0->g218(last-use) R1_L->g219(last-use) R6_S=g204->g220(last-use)
Anti: %R0_L<def> = ANDLri %R0_L<kill>, 2047, pred:8, pred:%noreg
Def Groups: R0_L=g208->g209(via R0_S)->g218(via R0_D)->g210(via R1_S)->g210(via R0_D)
Antidep reg: R0_L (real dependency)
Use Groups: R0_L=g210
Anti: %R1_L<def> = ANDLri %R1_L<kill>, 2047, pred:8, pred:%noreg
Def Groups: R1_L=g219->g210(via R0_D)
Antidep reg: R1_L (real dependency)
Use Groups: R1_L=g210
Anti: %R0_L<def> = LSRLrr %R2_L, %R0_S, pred:8, pred:%noreg, %R0_L<imp-use,kill>
Def Groups: R0_L=g210->g210(via R0_D)->g210(via R0_D)
Antidep reg: R0_L Use Groups: R2_L=g192 R0_S=g210 R0_L=g210
Anti: %R1_L<def> = LSRLrr %R1_L<kill>, %R0_S, pred:8, pred:%noreg
Def Groups: R1_L=g210->g210(via R0_D)
Antidep reg: R1_L Use Groups: R1_L=g210 R0_S=g210
Anti: %R0_L<def> = TRLi9 16, pred:8, pred:%noreg
Def Groups: R0_L=g210->g210(via R0_D)->g210(via R0_D)
Antidep reg: R0_L
Rename Candidates for Group g210:
R0_D: elcInt64Regs :: R0_D R1_D R2_D R3_D R4_D R5_D R8_D R9_D R10_D R11_D R12_D R13_D R14_D R15_D R16_D R17_D R18_D R19_D R20_D R21_D R22_D R23_D R24_D R25_D
R0_L: elcIntRegs elcIntAIRegs elcIntRegs elcIntRegs elcIntRegs elcIntRegs :: R0_L R1_L R2_L R3_L R4_L R5_L R8_L R9_L R10_L R11_L R12_L R13_L R14_L R15_L R16_L R17_L R18_L R19_L R20_L R21_L R22_L R23_L R24_L R25_L
R1_L: elcIntRegs elcIntRegs elcIntRegs elcIntRegs elcIntRegs :: R0_L R1_L R2_L R3_L R4_L R5_L R8_L R9_L R10_L R11_L R12_L R13_L R14_L R15_L R16_L R17_L R18_L R19_L R20_L R21_L R22_L R23_L R24_L R25_L
R0_S: elcShrtRegs elcShrtRegs :: R0_S R1_S R2_S R3_S R4_S R5_S R8_S R9_S R10_S R11_S R12_S R13_S R14_S R15_S R16_S R17_S R18_S R19_S R20_S R21_S R22_S R23_S R24_S R25_S
Find Registers: [R12_D: R12_D R12_L R13_L R12_S]
Breaking anti-dependence edge on R0_L: R0_D->R12_D(1 refs) R0_L->R12_L(7 refs) R1_L->R13_L(5 refs) R0_S->R12_S(2 refs)
Use Groups:
...
%R12_L<def> = TRLi9 16, pred:8, pred:%noreg
%R13_L<def> = LSRLrr %R13_L<kill>, %R12_S, pred:8, pred:%noreg
%R12_L<def> = LSRLrr %R2_L<kill>, %R12_S<kill>, pred:8, pred:%noreg, %R12_L<imp-use,kill>
%R13_L<def> = ANDLri %R13_L<kill>, 2047, pred:8, pred:%noreg
%R12_L<def> = ANDLri %R12_L<kill>, 2047, pred:8, pred:%noreg
%R4_D<def> = ASRDrr %R12_D, %R6_S, %R12_L<imp-def>, %R12_S<imp-def>, %R13_S<imp-def>
As demonstrated by this example, this is also somewhat unfortunate, because
there is actually no need to rename the super register in this case (it is
fully covered by later subregister definitions), but we don't seem to track
enough information here to exploit that either.
Thanks to Daniil Troshkov for reporting the issue. The debug outputs in this
commit message are from Daniil.
Modified:
llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=227311&r1=227310&r2=227311&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Wed Jan 28 08:44:14 2015
@@ -296,6 +296,16 @@ void AggressiveAntiDepBreaker::HandleLas
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
+ // FIXME: We must leave subregisters of live super registers as live, so that
+ // we don't clear out the register tracking information for subregisters of
+ // super registers we're still tracking (and with which we're unioning
+ // subregister definitions).
+ for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
+ if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
+ DEBUG(if (!header && footer) dbgs() << footer);
+ return;
+ }
+
if (!State->IsLive(Reg)) {
KillIndices[Reg] = KillIdx;
DefIndices[Reg] = ~0u;
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