[llvm] r227293 - Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.
Eric Christopher
echristo at gmail.com
Tue Jan 27 19:51:33 PST 2015
Author: echristo
Date: Tue Jan 27 21:51:33 2015
New Revision: 227293
URL: http://llvm.org/viewvc/llvm-project?rev=227293&view=rev
Log:
Migrate AArch64 except for TTI and AsmPrinter away from getSubtargetImpl.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp
llvm/trunk/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp Tue Jan 27 21:51:33 2015
@@ -376,10 +376,8 @@ bool AArch64AdvSIMDScalar::runOnMachineF
bool Changed = false;
DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
- const TargetMachine &TM = mf.getTarget();
MRI = &mf.getRegInfo();
- TII = static_cast<const AArch64InstrInfo *>(
- TM.getSubtargetImpl()->getInstrInfo());
+ TII = static_cast<const AArch64InstrInfo *>(mf.getSubtarget().getInstrInfo());
// Just check things on a one-block-at-a-time basis.
for (MachineFunction::iterator I = mf.begin(), E = mf.end(); I != E; ++I)
Modified: llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp Tue Jan 27 21:51:33 2015
@@ -476,9 +476,7 @@ bool AArch64BranchRelaxation::runOnMachi
DEBUG(dbgs() << "***** AArch64BranchRelaxation *****\n");
- TII = (const AArch64InstrInfo *)MF->getTarget()
- .getSubtargetImpl()
- ->getInstrInfo();
+ TII = (const AArch64InstrInfo *)MF->getSubtarget().getInstrInfo();
// Renumber all of the machine basic blocks in the function, guaranteeing that
// the numbers agree with the position of the block in the function.
Modified: llvm/trunk/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp Tue Jan 27 21:51:33 2015
@@ -92,9 +92,8 @@ struct LDTLSCleanup : public MachineFunc
MachineInstr *replaceTLSBaseAddrCall(MachineInstr *I,
unsigned TLSBaseAddrReg) {
MachineFunction *MF = I->getParent()->getParent();
- const AArch64TargetMachine *TM =
- static_cast<const AArch64TargetMachine *>(&MF->getTarget());
- const AArch64InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
+ const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>(
+ MF->getSubtarget().getInstrInfo());
// Insert a Copy from TLSBaseAddrReg to x0, which is where the rest of the
// code sequence assumes the address will be.
@@ -112,9 +111,8 @@ struct LDTLSCleanup : public MachineFunc
// inserting a copy instruction after I. Returns the new instruction.
MachineInstr *setRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
MachineFunction *MF = I->getParent()->getParent();
- const AArch64TargetMachine *TM =
- static_cast<const AArch64TargetMachine *>(&MF->getTarget());
- const AArch64InstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
+ const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>(
+ MF->getSubtarget().getInstrInfo());
// Create a virtual register for the TLS base address.
MachineRegisterInfo &RegInfo = MF->getRegInfo();
Modified: llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp Tue Jan 27 21:51:33 2015
@@ -285,9 +285,7 @@ static void initReachingDef(MachineFunct
BlockToSetOfInstrsPerColor &ReachableUses,
const MapRegToId &RegToId,
const MachineInstr *DummyOp, bool ADRPMode) {
- const TargetMachine &TM = MF.getTarget();
- const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
-
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
unsigned NbReg = RegToId.size();
for (MachineBasicBlock &MBB : MF) {
@@ -1026,8 +1024,7 @@ static void collectInvolvedReg(MachineFu
}
bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
- const TargetMachine &TM = MF.getTarget();
- const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
const MachineDominatorTree *MDT = &getAnalysis<MachineDominatorTree>();
MapRegToId RegToId;
@@ -1043,8 +1040,8 @@ bool AArch64CollectLOH::runOnMachineFunc
MachineInstr *DummyOp = nullptr;
if (BasicBlockScopeOnly) {
- const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>(
- TM.getSubtargetImpl()->getInstrInfo());
+ const AArch64InstrInfo *TII =
+ static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
// For local analysis, create a dummy operation to record uses that are not
// local.
DummyOp = MF.CreateMachineInstr(TII->get(AArch64::COPY), DebugLoc());
Modified: llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp Tue Jan 27 21:51:33 2015
@@ -304,7 +304,7 @@ bool AArch64ConditionOptimizer::adjustTo
bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
<< "********** Function: " << MF.getName() << '\n');
- TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();
+ TII = MF.getSubtarget().getInstrInfo();
DomTree = &getAnalysis<MachineDominatorTree>();
bool Changed = false;
Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Tue Jan 27 21:51:33 2015
@@ -3325,7 +3325,7 @@ bool AArch64FastISel::fastLowerIntrinsic
const AArch64RegisterInfo *RegInfo =
static_cast<const AArch64RegisterInfo *>(
- TM.getSubtargetImpl()->getRegisterInfo());
+ FuncInfo.MF->getSubtarget().getRegisterInfo());
unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Jan 27 21:51:33 2015
@@ -878,9 +878,8 @@ AArch64TargetLowering::EmitF128CSEL(Mach
// EndBB:
// Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
- const TargetInstrInfo *TII =
- getTargetMachine().getSubtargetImpl()->getInstrInfo();
MachineFunction *MF = MBB->getParent();
+ const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
const BasicBlock *LLVM_BB = MBB->getBasicBlock();
DebugLoc DL = MI->getDebugLoc();
MachineFunction::iterator It = MBB;
@@ -2797,19 +2796,17 @@ AArch64TargetLowering::LowerCall(CallLow
// Add a register mask operand representing the call-preserved registers.
const uint32_t *Mask;
- const TargetRegisterInfo *TRI =
- getTargetMachine().getSubtargetImpl()->getRegisterInfo();
- const AArch64RegisterInfo *ARI =
- static_cast<const AArch64RegisterInfo *>(TRI);
+ const AArch64RegisterInfo *TRI = static_cast<const AArch64RegisterInfo *>(
+ MF.getSubtarget().getRegisterInfo());
if (IsThisReturn) {
// For 'this' returns, use the X0-preserving mask if applicable
- Mask = ARI->getThisReturnPreservedMask(CallConv);
+ Mask = TRI->getThisReturnPreservedMask(CallConv);
if (!Mask) {
IsThisReturn = false;
- Mask = ARI->getCallPreservedMask(CallConv);
+ Mask = TRI->getCallPreservedMask(CallConv);
}
} else
- Mask = ARI->getCallPreservedMask(CallConv);
+ Mask = TRI->getCallPreservedMask(CallConv);
assert(Mask && "Missing call preserved mask for calling convention");
Ops.push_back(DAG.getRegisterMask(Mask));
@@ -3029,11 +3026,9 @@ AArch64TargetLowering::LowerDarwinGlobal
// TLS calls preserve all registers except those that absolutely must be
// trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
// silly).
- const TargetRegisterInfo *TRI =
- getTargetMachine().getSubtargetImpl()->getRegisterInfo();
- const AArch64RegisterInfo *ARI =
- static_cast<const AArch64RegisterInfo *>(TRI);
- const uint32_t *Mask = ARI->getTLSCallPreservedMask();
+ const uint32_t *Mask =
+ static_cast<const AArch64RegisterInfo *>(
+ DAG.getSubtarget().getRegisterInfo())->getTLSCallPreservedMask();
// Finally, we can make the call. This is just a degenerate version of a
// normal AArch64 call node: x0 takes the address of the descriptor, and
@@ -3080,11 +3075,9 @@ SDValue AArch64TargetLowering::LowerELFT
// TLS calls preserve all registers except those that absolutely must be
// trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
// silly).
- const TargetRegisterInfo *TRI =
- getTargetMachine().getSubtargetImpl()->getRegisterInfo();
- const AArch64RegisterInfo *ARI =
- static_cast<const AArch64RegisterInfo *>(TRI);
- const uint32_t *Mask = ARI->getTLSCallPreservedMask();
+ const uint32_t *Mask =
+ static_cast<const AArch64RegisterInfo *>(
+ DAG.getSubtarget().getRegisterInfo())->getTLSCallPreservedMask();
// The function takes only one argument: the address of the descriptor itself
// in X0.
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Jan 27 21:51:33 2015
@@ -707,9 +707,8 @@ static bool UpdateOperandRegClass(Machin
assert(MBB && "Can't get MachineBasicBlock here");
MachineFunction *MF = MBB->getParent();
assert(MF && "Can't get MachineFunction here");
- const TargetMachine *TM = &MF->getTarget();
- const TargetInstrInfo *TII = TM->getSubtargetImpl()->getInstrInfo();
- const TargetRegisterInfo *TRI = TM->getSubtargetImpl()->getRegisterInfo();
+ const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
+ const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
MachineRegisterInfo *MRI = &MF->getRegInfo();
for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
Modified: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Tue Jan 27 21:51:33 2015
@@ -945,10 +945,8 @@ bool AArch64LoadStoreOpt::optimizeBlock(
}
bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
- const TargetMachine &TM = Fn.getTarget();
- TII = static_cast<const AArch64InstrInfo *>(
- TM.getSubtargetImpl()->getInstrInfo());
- TRI = TM.getSubtargetImpl()->getRegisterInfo();
+ TII = static_cast<const AArch64InstrInfo *>(Fn.getSubtarget().getInstrInfo());
+ TRI = Fn.getSubtarget().getRegisterInfo();
bool Modified = false;
for (auto &MBB : Fn)
Modified: llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp?rev=227293&r1=227292&r2=227293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp Tue Jan 27 21:51:33 2015
@@ -328,7 +328,7 @@ void A57ChainingConstraint::apply(PBQPRA
const MachineFunction &MF = G.getMetadata().MF;
LiveIntervals &LIs = G.getMetadata().LIS;
- TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo();
+ TRI = MF.getSubtarget().getRegisterInfo();
DEBUG(MF.dump());
for (const auto &MBB: MF) {
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