[PATCH] [mips][microMIPS] Implement LWGP instruction

[Sasa Stankovic]

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:824
@@ -823,2 +823,3 @@
     return isMem() && getMemBase()->isMM16AsmReg();
   }
+  template <unsigned Bits> bool isMemWithUimmOffsetGP() const {
----------------
This method is not used (if I comment it out, the tests still pass). I think that you also don't need MicroMipsMemGPAsmOperand parser match class.

================
Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:1272
@@ +1271,3 @@
+              getContext().getRegisterInfo()->getRegClass(
+                Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
+              BaseReg.getReg() == Mips::GP) {
----------------
You should additionally check that the instruction is not a store, because there is no 16-bit gp-relative store instruction. For example, for the following instruction

sw      $3, 32($gp)

instead of emitting 32-bit store instruction, the 16-bit load is emitted. Please add this instruction to the tests.

http://reviews.llvm.org/D6650

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