[llvm] r226945 - R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()

[Tom Stellard]

Hi Hans,

Is this OK to merge to the 3.6 branch?  It fixes and infinite loop
when legalizing misaligned loads.

I am the code owner and I approve this patch.

-Tom

On Fri, Jan 23, 2015 at 10:05:45PM -0000, Tom Stellard wrote:
> Author: tstellar
> Date: Fri Jan 23 16:05:45 2015
> New Revision: 226945
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=226945&view=rev
> Log:
> R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()
> 
> We used to do this promotion during DAG legalization, but this
> caused an infinite loop in ExpandUnalignedLoad() because it assumed
> that i64 loads were legal if i64 was a legal type.
> 
> It also seems better to report i64 loads as legal, since they actually
> are and we were just promoting them to simplify our tablegen files.
> 
> Added:
>     llvm/trunk/test/CodeGen/R600/misaligned-load.ll
> Modified:
>     llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
>     llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp?rev=226945&r1=226944&r2=226945&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelDAGToDAG.cpp Fri Jan 23 16:05:45 2015
> @@ -417,6 +417,28 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNod
>                                    N->getValueType(0), Ops);
>    }
>  
> +  case ISD::LOAD: {
> +    // To simplify the TableGen patters, we replace all i64 loads with
> +    // v2i32 loads.  Alternatively, we could promote i64 loads to v2i32
> +    // during DAG legalization, however, so places (ExpandUnalignedLoad)
> +    // in the DAG legalizer assume that if i64 is legal, so doing this
> +    // promotion early can cause problems.
> +    EVT VT = N->getValueType(0);
> +    LoadSDNode *LD = cast<LoadSDNode>(N);
> +    if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD)
> +      break;
> +
> +    SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SDLoc(N), LD->getChain(),
> +                                     LD->getBasePtr(), LD->getMemOperand());
> +    SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
> +                                      MVT::i64, NewLoad);
> +    CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLoad.getValue(1));
> +    CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), BitCast);
> +    SelectCode(NewLoad.getNode());
> +    N = BitCast.getNode();
> +    break;
> +  }
> +
>    case AMDGPUISD::REGISTER_LOAD: {
>      if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
>        break;
> 
> Modified: llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp?rev=226945&r1=226944&r2=226945&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUISelLowering.cpp Fri Jan 23 16:05:45 2015
> @@ -189,9 +189,6 @@ AMDGPUTargetLowering::AMDGPUTargetLoweri
>    setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
>    AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
>  
> -  setOperationAction(ISD::LOAD, MVT::i64, Promote);
> -  AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
> -
>    setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
>    AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
>  
> 
> Added: llvm/trunk/test/CodeGen/R600/misaligned-load.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/misaligned-load.ll?rev=226945&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/misaligned-load.ll (added)
> +++ llvm/trunk/test/CodeGen/R600/misaligned-load.ll Fri Jan 23 16:05:45 2015
> @@ -0,0 +1,18 @@
> +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
> +
> +; SI: @byte_aligned_load64
> +; SI: ds_read_u8
> +; SI: ds_read_u8
> +; SI: ds_read_u8
> +; SI: ds_read_u8
> +; SI: ds_read_u8
> +; SI: ds_read_u8
> +; SI: ds_read_u8
> +; SI: ds_read_u8
> +; SI: s_endpgm
> +define void @byte_aligned_load64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) {
> +entry:
> +  %0 = load i64 addrspace(3)* %in, align 1
> +  store i64 %0, i64 addrspace(1)* %out
> +  ret void
> +}
> 
> 
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