[PATCH] [mips] Add tests for bitwise binary and integer arithmetic operators.

[Daniel Sanders]

Thanks for doing this. It seems that we have a lot of optimization deficiencies on basic operations that we need to sort out. In particular, we emit a lot of unnecessary sign/zero extends. I pointed out a few but stopped after I realized how often it occurred.

LGTM with the nits below fixed. If you can also annotate the redundant instructions with FIXME's that would be appreciated but there's a lot so I'm not going to make that a requirement.


================
Comment at: test/CodeGen/Mips/llvm-ir/ashr.ll:31
@@ +30,3 @@
+entry:
+; all-label: ashr_i1:
+
----------------
all-label should be ALL-LABEL. Likewise below

================
Comment at: test/CodeGen/Mips/llvm-ir/ashr.ll:43
@@ +42,3 @@
+
+  ; ALL:        andi    $[[T0:[0-9]+]], $5, 255
+  ; ALL:        srav    $2, $4, $[[T0]]
----------------
The andi's are redundant in this file. Please add a FIXME about this

================
Comment at: test/CodeGen/Mips/llvm-ir/ashr.ll:120
@@ +119,3 @@
+
+  ; GP64:       sll       $[[T0:[0-9]+]], $5, 0
+  ; GP64:       dsrav     $2, $4, $[[T0]]
----------------
This should be redundant too. Please add a FIXME

================
Comment at: test/CodeGen/Mips/llvm-ir/lshr.ll:43-52
@@ +42,12 @@
+
+  ; NOT-R2-R6:    andi    $[[T0:[0-9]+]], $5, 255
+  ; NOT-R2-R6:    andi    $[[T1:[0-9]+]], $4, 255
+  ; NOT-R2-R6:    srlv    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; NOT-R2-R6:    sll     $[[T3:[0-9]+]], $[[T2]], 24
+  ; NOT-R2-R6:    sra     $2, $[[T3]], 24
+
+  ; R2-R6:        andi    $[[T0:[0-9]+]], $5, 255
+  ; R2-R6:        andi    $[[T1:[0-9]+]], $4, 255
+  ; R2-R6:        srlv    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+  ; R2-R6:        seb     $2, $[[T2]]
+
----------------
It would be good to eliminate the excess instructions by changing the signext's to zeroext.
We'll have other tests for sign/zero extension.

Likewise below

================
Comment at: test/CodeGen/Mips/llvm-ir/or.ll:57
@@ +56,3 @@
+  ; GP64:         or     $[[T0:[0-9]+]], $4, $5
+  ; GP64:         sll     $2, $[[T0]], 0
+
----------------
This is redundant.

================
Comment at: test/CodeGen/Mips/llvm-ir/sdiv.ll:27-28
@@ +26,4 @@
+  ; NOT-R6:       mflo    $[[T0:[0-9]+]]
+  ; NOT-R6:       sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; NOT-R6:       sra     $2, $[[T1]], 31
+
----------------
These should be redundant since div is signed.
Likewise below

================
Comment at: test/CodeGen/Mips/llvm-ir/udiv.ll:20
@@ +19,3 @@
+
+define signext i1 @udiv_i1(i1 signext %a, i1 signext %b) {
+entry:
----------------
It would be good to eliminate the sign extends by switching to zeroext.

http://reviews.llvm.org/D7125

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