[llvm] r226805 - Fixed a bug in narrowing store operation.

[Demikhovsky, Elena]

Fixed, thank you.

-  Elena


-----Original Message-----
From: İsmail Dönmez [mailto:ismail at donmez.ws] 
Sent: Thursday, January 22, 2015 11:46
To: Demikhovsky, Elena
Cc: llvm-commits
Subject: Re: [llvm] r226805 - Fixed a bug in narrowing store operation.

Hi,

On Thu, Jan 22, 2015 at 11:39 AM, Elena Demikhovsky <elena.demikhovsky at intel.com> wrote:
> Author: delena
> Date: Thu Jan 22 03:39:08 2015
> New Revision: 226805
>
> URL: http://llvm.org/viewvc/llvm-project?rev=226805&view=rev
> Log:
> Fixed a bug in narrowing store operation.
> Type MVT::i1 became legal in KNL, but store operation can't be 
> narrowed to this type, since the size of VT (1 bit) is not equal to its actual store size(8 bits).
>
> Added a test provided by David (dag at cray.com)
>
> Added:
>     llvm/trunk/test/CodeGen/X86/i1narrowfail.ll
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: 
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDA
> G/DAGCombiner.cpp?rev=226805&r1=226804&r2=226805&view=diff
> ======================================================================
> ========
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 22 
> +++ 03:39:08 2015
> @@ -9497,9 +9497,12 @@ SDValue DAGCombiner::ReduceLoadOpStoreWi
>      unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
>      unsigned NewBW = NextPowerOf2(MSB - ShAmt);
>      EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
> +    // The narowwing should be profitable, the load/store operation 
> + should be

Typo here, should be s/narowwing/narrowing

ismail
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