[PATCH] R600/SI: Also enable WQM for image opcodes which calculate LOD

[Tom Stellard]

On Wed, Jan 21, 2015 at 01:07:25PM +0900, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
> 
> If whole quad mode isn't enabled for these, the level of detail is
> calculated incorrectly for pixels along diagonal triangle edges, causing
> artifacts.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
> ---
>  lib/Target/R600/SILowerControlFlow.cpp | 55 ++++++++++++++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
> 
> diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
> index 068b22f..a468a18 100644
> --- a/lib/Target/R600/SILowerControlFlow.cpp
> +++ b/lib/Target/R600/SILowerControlFlow.cpp
> @@ -514,6 +514,61 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
>            IndirectDst(MI);
>            break;
>  
> +#define MATCH_IMAGE(opcode)                   \
> +        case AMDGPU::IMAGE_##opcode##_V1_V1:  \
> +        case AMDGPU::IMAGE_##opcode##_V1_V2:  \
> +        case AMDGPU::IMAGE_##opcode##_V1_V4:  \
> +        case AMDGPU::IMAGE_##opcode##_V1_V8:  \
> +        case AMDGPU::IMAGE_##opcode##_V1_V16: \
> +        case AMDGPU::IMAGE_##opcode##_V2_V1:  \
> +        case AMDGPU::IMAGE_##opcode##_V2_V2:  \
> +        case AMDGPU::IMAGE_##opcode##_V2_V4:  \
> +        case AMDGPU::IMAGE_##opcode##_V2_V8:  \
> +        case AMDGPU::IMAGE_##opcode##_V2_V16: \
> +        case AMDGPU::IMAGE_##opcode##_V3_V1:  \
> +        case AMDGPU::IMAGE_##opcode##_V3_V2:  \
> +        case AMDGPU::IMAGE_##opcode##_V3_V4:  \
> +        case AMDGPU::IMAGE_##opcode##_V3_V8:  \
> +        case AMDGPU::IMAGE_##opcode##_V3_V16: \
> +        case AMDGPU::IMAGE_##opcode##_V4_V1:  \
> +        case AMDGPU::IMAGE_##opcode##_V4_V2:  \
> +        case AMDGPU::IMAGE_##opcode##_V4_V4:  \
> +        case AMDGPU::IMAGE_##opcode##_V4_V8:  \
> +        case AMDGPU::IMAGE_##opcode##_V4_V16
> +
> +        MATCH_IMAGE(GATHER4):
> +        MATCH_IMAGE(GATHER4_B):
> +        MATCH_IMAGE(GATHER4_B_CL):
> +        MATCH_IMAGE(GATHER4_B_CL_O):
> +        MATCH_IMAGE(GATHER4_B_O):
> +        MATCH_IMAGE(GATHER4_C):
> +        MATCH_IMAGE(GATHER4_C_B):
> +        MATCH_IMAGE(GATHER4_C_B_CL):
> +        MATCH_IMAGE(GATHER4_C_B_CL_O):
> +        MATCH_IMAGE(GATHER4_C_B_O):
> +        MATCH_IMAGE(GATHER4_C_CL):
> +        MATCH_IMAGE(GATHER4_C_CL_O):
> +        MATCH_IMAGE(GATHER4_C_O):
> +        MATCH_IMAGE(GATHER4_CL):
> +        MATCH_IMAGE(GATHER4_CL_O):
> +        MATCH_IMAGE(GATHER4_O):
> +        MATCH_IMAGE(GET_LOD):
> +        MATCH_IMAGE(SAMPLE):
> +        MATCH_IMAGE(SAMPLE_B):
> +        MATCH_IMAGE(SAMPLE_B_CL):
> +        MATCH_IMAGE(SAMPLE_B_CL_O):
> +        MATCH_IMAGE(SAMPLE_B_O):
> +        MATCH_IMAGE(SAMPLE_C):
> +        MATCH_IMAGE(SAMPLE_C_B):
> +        MATCH_IMAGE(SAMPLE_C_B_CL):
> +        MATCH_IMAGE(SAMPLE_C_B_CL_O):
> +        MATCH_IMAGE(SAMPLE_C_B_O):
> +        MATCH_IMAGE(SAMPLE_C_CL):
> +        MATCH_IMAGE(SAMPLE_C_CL_O):
> +        MATCH_IMAGE(SAMPLE_C_O):
> +        MATCH_IMAGE(SAMPLE_CL):
> +        MATCH_IMAGE(SAMPLE_CL_O):
> +        MATCH_IMAGE(SAMPLE_O):

Would it be possible to avoid this switch statement by adding a
new target flag to these tablegen definitions?


-Tom

>          case AMDGPU::V_INTERP_P1_F32:
>          case AMDGPU::V_INTERP_P2_F32:
>          case AMDGPU::V_INTERP_MOV_F32:
> -- 
> 2.1.4
> 
> 
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