[compiler-rt] r226567 - [MIPS64] Make __clear_cache more optimal

[Petar Jovanovic]

Author: petarj
Date: Tue Jan 20 09:04:19 2015
New Revision: 226567

URL: http://llvm.org/viewvc/llvm-project?rev=226567&view=rev
Log:
[MIPS64] Make __clear_cache more optimal

Use synci implementation of clear_cache for short address ranges.
For long address ranges, make a kernel call.

Differential Revision: http://reviews.llvm.org/D6661

Modified:
    compiler-rt/trunk/lib/builtins/clear_cache.c

Modified: compiler-rt/trunk/lib/builtins/clear_cache.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/builtins/clear_cache.c?rev=226567&r1=226566&r2=226567&view=diff
==============================================================================
--- compiler-rt/trunk/lib/builtins/clear_cache.c (original)
+++ compiler-rt/trunk/lib/builtins/clear_cache.c Tue Jan 20 09:04:19 2015
@@ -24,6 +24,51 @@
 
 #if defined(__ANDROID__) && defined(__mips__)
   #include <sys/cachectl.h>
+  #include <sys/syscall.h>
+  #ifdef __LP64__
+    /*
+     * clear_mips_cache - Invalidates instruction cache for Mips.
+     */
+    static void clear_mips_cache(const void* Addr, size_t Size) {
+      asm volatile (
+        ".set push\n"
+        ".set noreorder\n"
+        ".set noat\n"
+        "beq %[Size], $zero, 20f\n"          /* If size == 0, branch around. */
+        "nop\n"
+        "daddu %[Size], %[Addr], %[Size]\n"  /* Calculate end address + 1 */
+        "rdhwr $v0, $1\n"                    /* Get step size for SYNCI.
+                                                $1 is $HW_SYNCI_Step */
+        "beq $v0, $zero, 20f\n"              /* If no caches require
+                                                synchronization, branch
+                                                around. */
+        "nop\n"
+        "10:\n"
+        "synci 0(%[Addr])\n"                 /* Synchronize all caches around
+                                                address. */
+        "daddu %[Addr], %[Addr], $v0\n"      /* Add step size. */
+        "sltu $at, %[Addr], %[Size]\n"       /* Compare current with end
+                                                address. */
+        "bne $at, $zero, 10b\n"              /* Branch if more to do. */
+        "nop\n"
+        "sync\n"                             /* Clear memory hazards. */
+        "20:\n"
+        "bal 30f\n"
+        "nop\n"
+        "30:\n"
+        "daddiu $ra, $ra, 12\n"              /* $ra has a value of $pc here.
+                                                Add offset of 12 to point to the
+                                                instruction after the last nop.
+                                              */
+        "jr.hb $ra\n"                        /* Return, clearing instruction
+                                                hazards. */
+        "nop\n"
+        ".set pop\n"
+        : [Addr] "+r"(Addr), [Size] "+r"(Size)
+        :: "at", "ra", "v0", "memory"
+      );
+    }
+  #endif
 #endif
 
 #if defined(__ANDROID__) && defined(__arm__)
@@ -67,7 +112,17 @@ void __clear_cache(void *start, void *en
 #elif defined(__ANDROID__) && defined(__mips__)
   const uintptr_t start_int = (uintptr_t) start;
   const uintptr_t end_int = (uintptr_t) end;
-  _flush_cache(start, (end_int - start_int), BCACHE);
+    #ifdef __LP64__
+        // Call synci implementation for short address range.
+        const uintptr_t address_range_limit = 256;
+        if ((end_int - start_int) <= address_range_limit) {
+            clear_mips_cache(start, (end_int - start_int));
+        } else {
+            syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
+        }
+    #else
+        syscall(__NR_cacheflush, start, (end_int - start_int), BCACHE);
+    #endif
 #elif defined(__aarch64__) && !defined(__APPLE__)
   uint64_t xstart = (uint64_t)(uintptr_t) start;
   uint64_t xend = (uint64_t)(uintptr_t) end;