[PATCH] [ARM] Fix issue with SMLAL (Signed Multiply Accumulate Long) lowering

[Jyoti Allur]

Hi Tim,
The rationale behind my thinking was that there would never be a case where we need to update the same LoMul and LowAdd variables
consecutively, but as you said, it could be a wrong assumption. I am finding it hard to imagine a case though.
I have updated by adding appropriate checks to ensure LoMul and LowAdd variables are updated with its linked ISD::SMUL_LOHI node results
Thanks for reviewing.


REPOSITORY
  rL LLVM

http://reviews.llvm.org/D6998

Files:
  ../llvm/lib/Target/ARM/ARMISelLowering.cpp
  ../llvm/test/CodeGen/ARM/longMAC.ll

Index: ../llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- ../llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ ../llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8075,12 +8075,14 @@
   else
     HiAdd = &AddeOp0;
 
+  // When both operands of ADDC are a result from different ISD::SMUL_LOHI,
+  // make sure LoMul and LowAdd are taken from correct ISD::SMUL_LOHI result.
 
-  if (AddcOp0->getOpcode() == Opc) {
+  if ((AddcOp0->getOpcode() == Opc) && AddcOp0.getNode() == MULOp.getNode()) {
     LoMul = &AddcOp0;
     LowAdd = &AddcOp1;
   }
-  if (AddcOp1->getOpcode() == Opc) {
+  if ((AddcOp1->getOpcode() == Opc) && AddcOp1.getNode() == MULOp.getNode()) {
     LoMul = &AddcOp1;
     LowAdd = &AddcOp0;
   }
Index: ../llvm/test/CodeGen/ARM/longMAC.ll
===================================================================
--- ../llvm/test/CodeGen/ARM/longMAC.ll
+++ ../llvm/test/CodeGen/ARM/longMAC.ll
@@ -75,3 +75,18 @@
   %add = add i64 %mul, %c
   ret i64 %add
 }
+
+define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) {
+;CHECK-LABEL: MACLongTest6:
+;CHECK: smull   r12, lr, r1, r0
+;CHECK: smlal   r12, lr, r3, r2
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %mul = mul nsw i64 %conv1, %conv
+  %conv2 = sext i32 %c to i64
+  %conv3 = sext i32 %d to i64
+  %mul4 = mul nsw i64 %conv3, %conv2
+  %add = add nsw i64 %mul4, %mul
+  ret i64 %add
+}
+

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