[PATCH][mips] Add registers and ALL check prefix to octeon test, case.
Kai Nacke
kai.nacke at redstar.de
Sun Jan 18 22:24:37 PST 2015
Hi Daniel!
I added the registers for the MIPS64 case in the remaining test cases and I also introduced the ALL check prefix.
Please review.
Regards,
Kai
-------------- next part --------------
From f6babb717e59eeb7a62f9abe9b2d1097239a23fc Mon Sep 17 00:00:00 2001
From: kai <kai at redstar.de>
Date: Sat, 17 Jan 2015 12:54:42 +0100
Subject: [PATCH 2/4] [mips] Add registers and ALL check prefix to octeon test
case.
No functional change.
---
test/CodeGen/Mips/octeon.ll | 46 ++++++++++++++++++---------------------------
1 file changed, 18 insertions(+), 28 deletions(-)
diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll
index f0218fc..ced36b4 100644
--- a/test/CodeGen/Mips/octeon.ll
+++ b/test/CodeGen/Mips/octeon.ll
@@ -1,15 +1,14 @@
-; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=OCTEON
-; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=MIPS64
+; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=ALL -check-prefix=OCTEON
+; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64
define i64 @addi64(i64 %a, i64 %b) nounwind {
entry:
-; OCTEON-LABEL: addi64:
+; ALL-LABEL: addi64:
; OCTEON: jr $ra
; OCTEON: baddu $2, $4, $5
-; MIPS64-LABEL: addi64:
-; MIPS64: daddu
-; MIPS64: jr
-; MIPS64: andi
+; MIPS64: daddu $1, $4, $5
+; MIPS64: jr $ra
+; MIPS64: andi $2, $1, 255
%add = add i64 %a, %b
%and = and i64 %add, 255
ret i64 %and
@@ -17,23 +16,21 @@ entry:
define i64 @mul(i64 %a, i64 %b) nounwind {
entry:
-; OCTEON-LABEL: mul:
+; ALL-LABEL: mul:
; OCTEON: jr $ra
; OCTEON: dmul $2, $4, $5
-; MIPS64-LABEL: mul:
-; MIPS64: dmult
-; MIPS64: jr
-; MIPS64: mflo
+; MIPS64: dmult $4, $5
+; MIPS64: jr $ra
+; MIPS64: mflo $2
%res = mul i64 %a, %b
ret i64 %res
}
define i64 @cmpeq(i64 %a, i64 %b) nounwind {
entry:
-; OCTEON-LABEL: cmpeq:
+; ALL-LABEL: cmpeq:
; OCTEON: jr $ra
; OCTEON: seq $2, $4, $5
-; MIPS64-LABEL: cmpeq:
; MIPS64: xor $1, $4, $5
; MIPS64: sltiu $1, $1, 1
; MIPS64: dsll $1, $1, 32
@@ -46,10 +43,9 @@ entry:
define i64 @cmpeqi(i64 %a) nounwind {
entry:
-; OCTEON-LABEL: cmpeqi:
+; ALL-LABEL: cmpeqi:
; OCTEON: jr $ra
; OCTEON: seqi $2, $4, 42
-; MIPS64-LABEL: cmpeqi:
; MIPS64: daddiu $1, $zero, 42
; MIPS64: xor $1, $4, $1
; MIPS64: sltiu $1, $1, 1
@@ -63,10 +59,9 @@ entry:
define i64 @cmpne(i64 %a, i64 %b) nounwind {
entry:
-; OCTEON-LABEL: cmpne:
+; ALL-LABEL: cmpne:
; OCTEON: jr $ra
; OCTEON: sne $2, $4, $5
-; MIPS64-LABEL: cmpne:
; MIPS64: xor $1, $4, $5
; MIPS64: sltu $1, $zero, $1
; MIPS64: dsll $1, $1, 32
@@ -79,10 +74,9 @@ entry:
define i64 @cmpnei(i64 %a) nounwind {
entry:
-; OCTEON-LABEL: cmpnei:
+; ALL-LABEL: cmpnei:
; OCTEON: jr $ra
; OCTEON: snei $2, $4, 42
-; MIPS64-LABEL: cmpnei:
; MIPS64: daddiu $1, $zero, 42
; MIPS64: xor $1, $4, $1
; MIPS64: sltu $1, $zero, $1
@@ -96,9 +90,8 @@ entry:
define i64 @bbit0(i64 %a) nounwind {
entry:
-; OCTEON-LABEL: bbit0:
+; ALL-LABEL: bbit0:
; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]]
-; MIPS64-LABEL: bbit0:
; MIPS64: andi $1, $4, 8
; MIPS64: beqz $1, $[[BB0:BB[0-9_]+]]
%bit = and i64 %a, 8
@@ -113,9 +106,8 @@ endif:
define i64 @bbit032(i64 %a) nounwind {
entry:
-; OCTEON-LABEL: bbit032:
+; ALL-LABEL: bbit032:
; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
-; MIPS64-LABEL: bbit032:
; MIPS64: daddiu $1, $zero, 1
; MIPS64: dsll $1, $1, 35
; MIPS64: and $1, $4, $1
@@ -132,9 +124,8 @@ endif:
define i64 @bbit1(i64 %a) nounwind {
entry:
-; OCTEON-LABEL: bbit1:
+; ALL-LABEL: bbit1:
; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
-; MIPS64-LABEL: bbit1:
; MIPS64: andi $1, $4, 8
; MIPS64: beqz $1, $[[BB0:BB[0-9_]+]]
%bit = and i64 %a, 8
@@ -149,9 +140,8 @@ endif:
define i64 @bbit132(i64 %a) nounwind {
entry:
-; OCTEON-LABEL: bbit132:
+; ALL-LABEL: bbit132:
; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
-; MIPS64-LABEL: bbit132:
; MIPS64: daddiu $1, $zero, 1
; MIPS64: dsll $1, $1, 35
; MIPS64: and $1, $4, $1
--
1.9.4.msysgit.2
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