[llvm] r226326 - [Hexagon] Converting halfword to doubleword multiply intrinsics.
Colin LeMahieu
colinl at codeaurora.org
Fri Jan 16 13:41:58 PST 2015
Author: colinl
Date: Fri Jan 16 15:41:57 2015
New Revision: 226326
URL: http://llvm.org/viewvc/llvm-project?rev=226326&view=rev
Log:
[Hexagon] Converting halfword to doubleword multiply intrinsics.
Added:
llvm/trunk/test/CodeGen/Hexagon/intrinsics-mpyd.ll
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td?rev=226326&r1=226325&r2=226326&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td Fri Jan 16 15:41:57 2015
@@ -132,6 +132,39 @@ def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, i
def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
+
+//===----------------------------------------------------------------------===//
+// Multiply signed/unsigned halfwords with and without saturation and rounding
+// into a 64-bits destination register.
+//===----------------------------------------------------------------------===//
+
+def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
+def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
+def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
+def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
+def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
+def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
+def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
+def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
+
+def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
+def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
+def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
+def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
+def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
+def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
+def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
+def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
+
+def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
+def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
+def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
+def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
+def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
+def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
+def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
+def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
+
//
// ALU 32 types.
//
@@ -2685,43 +2718,6 @@ def HEXAGON_M2_dpmpyss_nac_s0:
* MTYPE/MPYS *
*********************************************************************/
-//Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]]
-def HEXAGON_M2_mpyd_hh_s0:
- di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>;
-def HEXAGON_M2_mpyd_hh_s1:
- di_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpyd_hh_s1>;
-def HEXAGON_M2_mpyd_rnd_hh_s1:
- di_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hh_s1>;
-def HEXAGON_M2_mpyd_rnd_hh_s0:
- di_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpyd_rnd_hh_s0>;
-
-def HEXAGON_M2_mpyd_hl_s0:
- di_MInst_sisi_hl <"mpy", int_hexagon_M2_mpyd_hl_s0>;
-def HEXAGON_M2_mpyd_hl_s1:
- di_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpyd_hl_s1>;
-def HEXAGON_M2_mpyd_rnd_hl_s1:
- di_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpyd_rnd_hl_s1>;
-def HEXAGON_M2_mpyd_rnd_hl_s0:
- di_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpyd_rnd_hl_s0>;
-
-def HEXAGON_M2_mpyd_lh_s0:
- di_MInst_sisi_lh <"mpy", int_hexagon_M2_mpyd_lh_s0>;
-def HEXAGON_M2_mpyd_lh_s1:
- di_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpyd_lh_s1>;
-def HEXAGON_M2_mpyd_rnd_lh_s1:
- di_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpyd_rnd_lh_s1>;
-def HEXAGON_M2_mpyd_rnd_lh_s0:
- di_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpyd_rnd_lh_s0>;
-
-def HEXAGON_M2_mpyd_ll_s0:
- di_MInst_sisi_ll <"mpy", int_hexagon_M2_mpyd_ll_s0>;
-def HEXAGON_M2_mpyd_ll_s1:
- di_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpyd_ll_s1>;
-def HEXAGON_M2_mpyd_rnd_ll_s1:
- di_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpyd_rnd_ll_s1>;
-def HEXAGON_M2_mpyd_rnd_ll_s0:
- di_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpyd_rnd_ll_s0>;
-
//Rx+=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]
def HEXAGON_M2_mpyd_acc_hh_s0:
di_MInst_disisi_acc_hh <"mpy", int_hexagon_M2_mpyd_acc_hh_s0>;
Added: llvm/trunk/test/CodeGen/Hexagon/intrinsics-mpyd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics-mpyd.ll?rev=226326&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics-mpyd.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics-mpyd.ll Fri Jan 16 15:41:57 2015
@@ -0,0 +1,270 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Verify that the mpy intrinsics are lowered into the right instructions.
+; These instructions have a 64-bit destination register.
+
+ at c = external global i64
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
+
+define void @test1(i32 %a1, i32 %b1) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.hh.s0(i32 %a1, i32 %b1)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.hh.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
+
+define void @test2(i32 %a2, i32 %b2) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.hl.s0(i32 %a2, i32 %b2)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.hl.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
+
+define void @test3(i32 %a3, i32 %b3) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.lh.s0(i32 %a3, i32 %b3)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.lh.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
+
+define void @test4(i32 %a4, i32 %b4) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.ll.s0(i32 %a4, i32 %b4)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.ll.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
+
+define void @test5(i32 %a5, i32 %b5) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.hh.s1(i32 %a5, i32 %b5)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.hh.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
+
+define void @test6(i32 %a6, i32 %b6) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.hl.s1(i32 %a6, i32 %b6)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.hl.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
+
+define void @test7(i32 %a7, i32 %b7) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.lh.s1(i32 %a7, i32 %b7)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.lh.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
+
+define void @test8(i32 %a8, i32 %b8) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.ll.s1(i32 %a8, i32 %b8)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):rnd
+
+define void @test9(i32 %a9, i32 %b9) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32 %a9, i32 %b9)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):rnd
+
+define void @test10(i32 %a10, i32 %b10) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32 %a10, i32 %b10)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):rnd
+
+define void @test11(i32 %a11, i32 %b11) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32 %a11, i32 %b11)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):rnd
+
+define void @test12(i32 %a12, i32 %b12) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32 %a12, i32 %b12)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd
+
+define void @test13(i32 %a13, i32 %b13) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32 %a13, i32 %b13)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hh.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd
+
+define void @test14(i32 %a14, i32 %b14) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32 %a14, i32 %b14)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.hl.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd
+
+define void @test15(i32 %a15, i32 %b15) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32 %a15, i32 %b15)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.lh.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd
+
+define void @test16(i32 %a16, i32 %b16) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32 %a16, i32 %b16)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyd.rnd.ll.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
+
+define void @test17(i32 %a17, i32 %b17) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.hh.s0(i32 %a17, i32 %b17)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.hh.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
+
+define void @test18(i32 %a18, i32 %b18) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.hl.s0(i32 %a18, i32 %b18)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.hl.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
+
+define void @test19(i32 %a19, i32 %b19) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.lh.s0(i32 %a19, i32 %b19)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.lh.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
+
+define void @test20(i32 %a20, i32 %b20) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.ll.s0(i32 %a20, i32 %b20)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.ll.s0(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
+
+define void @test21(i32 %a21, i32 %b21) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.hh.s1(i32 %a21, i32 %b21)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.hh.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
+
+define void @test22(i32 %a22, i32 %b22) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.hl.s1(i32 %a22, i32 %b22)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.hl.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
+
+define void @test23(i32 %a23, i32 %b23) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.lh.s1(i32 %a23, i32 %b23)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.lh.s1(i32, i32) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
+
+define void @test24(i32 %a24, i32 %b24) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.M2.mpyud.ll.s1(i32 %a24, i32 %b24)
+ store i64 %0, i64* @c, align 8
+ ret void
+}
+
+declare i64 @llvm.hexagon.M2.mpyud.ll.s1(i32, i32) #1
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