[llvm] r226155 - Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler.

[Craig Topper]

Author: ctopper
Date: Thu Jan 15 03:37:15 2015
New Revision: 226155

URL: http://llvm.org/viewvc/llvm-project?rev=226155&view=rev
Log:
Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrAVX512.td

Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=226155&r1=226154&r2=226155&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Thu Jan 15 03:37:15 2015
@@ -2113,7 +2113,7 @@ multiclass avx512_load_vl<bits<8> opc, s
 multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
                         ValueType OpVT, RegisterClass KRC, RegisterClass RC,
                         X86MemOperand memop, Domain d> {
-  let isAsmParserOnly = 1, hasSideEffects = 0 in {
+  let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
   def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
               !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
               EVEX;