[llvm] r226086 - Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"
Hal Finkel
hfinkel at anl.gov
Wed Jan 14 19:08:59 PST 2015
Author: hfinkel
Date: Wed Jan 14 21:08:59 2015
New Revision: 226086
URL: http://llvm.org/viewvc/llvm-project?rev=226086&view=rev
Log:
Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"
Reverting this while I investigate some bad behavior this is causing. As a
possibly-related issue, adding -verify-machineinstrs to one of the test cases
now fails because of this change:
llc test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll -march=x86-64 -o - -verify-machineinstrs
*** Bad machine code: No instruction at def index ***
- function: foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0) 0 at 784r 1 at 768r 2 at 752r 3 at 624r 4 at 480r 5 at 464r 6 at 336r 7 at 176r 8 at 160r 9 at 128r
- register: %DS
Valno #3 is defined at 624r
*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function: foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange: [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0) 0 at 784r 1 at 768r 2 at 752r 3 at 624r 4 at 480r 5 at 464r 6 at 336r 7 at 176r 8 at 160r 9 at 128r
- register: %DS
[624r,624d:3)
LLVM ERROR: Found 2 machine code errors.
where 624r corresponds exactly to the interval combining change:
624B %RSP<def> = COPY %vreg16; GR64:%vreg16
Considering merging %vreg16 with %RSP
RHS = %vreg16 [608r,624r:0) 0 at 608r
updated: 608B %RSP<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%saved_stack.1]
Success: %vreg16 -> %RSP
Result = %RSP
Modified:
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll
llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=226086&r1=226085&r2=226086&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Wed Jan 14 21:08:59 2015
@@ -1209,10 +1209,10 @@ bool RegisterCoalescer::canJoinPhys(cons
}
LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
- if (JoinVInt.containsOneValue())
+ if (CP.isFlipped() && JoinVInt.containsOneValue())
return true;
- DEBUG(dbgs() << "\tCannot join complex intervals into reserved register.\n");
+ DEBUG(dbgs() << "\tCannot join defs into reserved register.\n");
return false;
}
@@ -1431,7 +1431,8 @@ bool RegisterCoalescer::joinReservedPhys
LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n');
- assert(RHS.containsOneValue() && "Invalid join with reserved register");
+ assert(CP.isFlipped() && RHS.containsOneValue() &&
+ "Invalid join with reserved register");
// Optimization for reserved registers like ESP. We can only merge with a
// reserved physreg if RHS has a single value that is a copy of CP.DstReg().
@@ -1452,18 +1453,7 @@ bool RegisterCoalescer::joinReservedPhys
// defs are there.
// Delete the identity copy.
- MachineInstr *CopyMI;
- if (CP.isFlipped()) {
- CopyMI = MRI->getVRegDef(RHS.reg);
- } else {
- if (!MRI->hasOneNonDBGUse(RHS.reg)) {
- DEBUG(dbgs() << "\t\tMultiple vreg uses\n");
- return false;
- }
-
- CopyMI = &*MRI->use_instr_nodbg_begin(RHS.reg);
- }
-
+ MachineInstr *CopyMI = MRI->getVRegDef(RHS.reg);
LIS->RemoveMachineInstrFromMaps(CopyMI);
CopyMI->eraseFromParent();
Modified: llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll?rev=226086&r1=226085&r2=226086&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/dyn-stackalloc.ll Wed Jan 14 21:08:59 2015
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=generic -mtriple=arm-eabi < %s | FileCheck %s
+; RUN: llc -mtriple=arm-eabi %s -o /dev/null
%struct.comment = type { i8**, i32*, i32, i8* }
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
@@ -7,18 +7,6 @@
@str215 = external global [2 x i8]
define void @t1(%struct.state* %v) {
-
-; Make sure we generate:
-; sub sp, sp, r1
-; instead of:
-; sub r1, sp, r1
-; mov sp, r1
-
-; CHECK-LABEL: @t1
-; CHECK: bic [[REG1:r[0-9]+]],
-; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]]
-; CHECK: sub sp, sp, [[REG1]]
-
%tmp6 = load i32* null
%tmp8 = alloca float, i32 %tmp6
store i32 1, i32* null
Modified: llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll?rev=226086&r1=226085&r2=226086&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll Wed Jan 14 21:08:59 2015
@@ -1,19 +1,9 @@
; RUN: llc < %s
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64
; PR3538
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9"
define signext i8 @foo(i8* %s1) nounwind ssp {
-
-; Make sure we generate:
-; movq -40(%rbp), %rsp
-; Instead of:
-; movq -40(%rbp), %rax
-; movq %rax, %rsp
-
-; CHECK-LABEL: @foo
-; CHECK: movq -40(%rbp), %rsp
-
entry:
%s1_addr = alloca i8* ; <i8**> [#uses=2]
%retval = alloca i32 ; <i32*> [#uses=2]
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