[llvm] r226013 - [Hexagon] Removing old versions of cmph and updating references.
Colin LeMahieu
colinl at codeaurora.org
Wed Jan 14 10:26:14 PST 2015
Author: colinl
Date: Wed Jan 14 12:26:14 2015
New Revision: 226013
URL: http://llvm.org/viewvc/llvm-project?rev=226013&view=rev
Log:
[Hexagon] Removing old versions of cmph and updating references.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=226013&r1=226012&r2=226013&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Wed Jan 14 12:26:14 2015
@@ -554,7 +554,7 @@ CountValue *HexagonHardwareLoops::getLoo
break;
// Very limited support for byte/halfword compares.
case Hexagon::A4_cmpbeqi:
- case Hexagon::CMPhEQri_V4: {
+ case Hexagon::A4_cmpheqi: {
if (IVBump != 1)
return nullptr;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=226013&r1=226012&r2=226013&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Jan 14 12:26:14 2015
@@ -366,12 +366,11 @@ bool HexagonInstrInfo::analyzeCompare(co
SrcReg = MI->getOperand(1).getReg();
Mask = 0xFF;
break;
- case Hexagon::CMPhEQri_V4:
- case Hexagon::CMPhEQrr_shl_V4:
- case Hexagon::CMPhEQrr_xor_V4:
- case Hexagon::CMPhGTUri_V4:
- case Hexagon::CMPhGTUrr_V4:
- case Hexagon::CMPhGTrr_shl_V4:
+ case Hexagon::A4_cmpheqi:
+ case Hexagon::A4_cmpheq:
+ case Hexagon::A4_cmphgtui:
+ case Hexagon::A4_cmphgtu:
+ case Hexagon::A4_cmphgt:
SrcReg = MI->getOperand(1).getReg();
Mask = 0xFFFF;
break;
@@ -388,10 +387,9 @@ bool HexagonInstrInfo::analyzeCompare(co
case Hexagon::A4_cmpbeq:
case Hexagon::A4_cmpbgtu:
case Hexagon::A4_cmpbgt:
- case Hexagon::CMPhEQrr_shl_V4:
- case Hexagon::CMPhEQrr_xor_V4:
- case Hexagon::CMPhGTUrr_V4:
- case Hexagon::CMPhGTrr_shl_V4:
+ case Hexagon::A4_cmpheq:
+ case Hexagon::A4_cmphgtu:
+ case Hexagon::A4_cmphgt:
SrcReg2 = MI->getOperand(2).getReg();
return true;
@@ -400,8 +398,8 @@ bool HexagonInstrInfo::analyzeCompare(co
case Hexagon::C2_cmpgti:
case Hexagon::A4_cmpbeqi:
case Hexagon::A4_cmpbgtui:
- case Hexagon::CMPhEQri_V4:
- case Hexagon::CMPhGTUri_V4:
+ case Hexagon::A4_cmpheqi:
+ case Hexagon::A4_cmphgtui:
SrcReg2 = 0;
Value = MI->getOperand(2).getImm();
return true;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=226013&r1=226012&r2=226013&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Wed Jan 14 12:26:14 2015
@@ -2924,100 +2924,6 @@ def : Pat <(i32 (zext (i1 (setult (i32 (
0, 1))>,
Requires<[HasV4T]>;
-// Following instruction is not being extended as it results into the incorrect
-// code for negative numbers.
-
-// Signed half compare(.eq) ri.
-// Pd=cmph.eq(Rs,#s8)
-let isCompare = 1, validSubTargets = HasV4SubT in
-def CMPhEQri_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, s8Imm:$src2),
- "$dst = cmph.eq($src1, #$src2)",
- [(set (i1 PredRegs:$dst), (seteq (and (i32 IntRegs:$src1), 65535),
- s8ImmPred:$src2))]>,
- Requires<[HasV4T]>;
-
-// Signed half compare(.eq) rr.
-// Case 1: xor + and, then compare:
-// r0=xor(r0,r1)
-// r0=and(r0,#0xffff)
-// p0=cmp.eq(r0,#0)
-// Pd=cmph.eq(Rs,Rt)
-let isCompare = 1, validSubTargets = HasV4SubT in
-def CMPhEQrr_xor_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2),
- "$dst = cmph.eq($src1, $src2)",
- [(set (i1 PredRegs:$dst), (seteq (and (xor (i32 IntRegs:$src1),
- (i32 IntRegs:$src2)),
- 65535), 0))]>,
- Requires<[HasV4T]>;
-
-// Signed half compare(.eq) rr.
-// Case 2: shift left 16 bits then compare:
-// r0=asl(r0,16)
-// r1=asl(r1,16)
-// p0=cmp.eq(r0,r1)
-// Pd=cmph.eq(Rs,Rt)
-let isCompare = 1, validSubTargets = HasV4SubT in
-def CMPhEQrr_shl_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2),
- "$dst = cmph.eq($src1, $src2)",
- [(set (i1 PredRegs:$dst),
- (seteq (shl (i32 IntRegs:$src1), (i32 16)),
- (shl (i32 IntRegs:$src2), (i32 16))))]>,
- Requires<[HasV4T]>;
-
-/* Incorrect Pattern -- immediate should be right shifted before being
-used in the cmph.gt instruction.
-// Signed half compare(.gt) ri.
-// Pd=cmph.gt(Rs,#s8)
-
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
-isCompare = 1, validSubTargets = HasV4SubT in
-def CMPhGTri_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, s8Ext:$src2),
- "$dst = cmph.gt($src1, #$src2)",
- [(set (i1 PredRegs:$dst),
- (setgt (shl (i32 IntRegs:$src1), (i32 16)),
- s8ExtPred:$src2))]>,
- Requires<[HasV4T]>;
-*/
-
-// Signed half compare(.gt) rr.
-// Pd=cmph.gt(Rs,Rt)
-let isCompare = 1, validSubTargets = HasV4SubT in
-def CMPhGTrr_shl_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2),
- "$dst = cmph.gt($src1, $src2)",
- [(set (i1 PredRegs:$dst),
- (setgt (shl (i32 IntRegs:$src1), (i32 16)),
- (shl (i32 IntRegs:$src2), (i32 16))))]>,
- Requires<[HasV4T]>;
-
-// Unsigned half compare rr (.gtu).
-// Pd=cmph.gtu(Rs,Rt)
-let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
-InputType = "reg" in
-def CMPhGTUrr_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, IntRegs:$src2),
- "$dst = cmph.gtu($src1, $src2)",
- [(set (i1 PredRegs:$dst),
- (setugt (and (i32 IntRegs:$src1), 65535),
- (and (i32 IntRegs:$src2), 65535)))]>,
- Requires<[HasV4T]>, ImmRegRel;
-
-// Unsigned half compare ri (.gtu).
-// Pd=cmph.gtu(Rs,#u7)
-let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 7,
-isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPhGTU",
-InputType = "imm" in
-def CMPhGTUri_V4 : MInst<(outs PredRegs:$dst),
- (ins IntRegs:$src1, u7Ext:$src2),
- "$dst = cmph.gtu($src1, #$src2)",
- [(set (i1 PredRegs:$dst), (setugt (and (i32 IntRegs:$src1), 65535),
- u7ExtPred:$src2))]>,
- Requires<[HasV4T]>, ImmRegRel;
-
let validSubTargets = HasV4SubT in
def NTSTBIT_rr : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
"$dst = !tstbit($src1, $src2)",
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