[llvm] r225968 - [mips] Refine octeon instructions seq/seqi/sne/snei

[Kai Nacke]

Author: redstar
Date: Wed Jan 14 04:19:09 2015
New Revision: 225968

URL: http://llvm.org/viewvc/llvm-project?rev=225968&view=rev
Log:
[mips] Refine octeon instructions seq/seqi/sne/snei

This commit refines the pattern for the octeon seq/seqi/sne/snei instructions.
The target register is set to 0 or 1 according to the result of the comparison.
In C, this is something like

rd = (unsigned long)(rs == rt)

This commit adds a zext to bring the result to i64. With this change the
instruction is selected for this type of code. (gcc produces the same code for
the above C code.)

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/octeon.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=225968&r1=225967&r2=225968&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Jan 14 04:19:09 2015
@@ -290,7 +290,8 @@ class ExtsCins<string opstr, SDPatternOp
 class SetCC64_R<string opstr, PatFrag cond_op> :
   InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
          !strconcat(opstr, "\t$rd, $rs, $rt"),
-         [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
+         [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
+                                             GPR64Opnd:$rt)))],
          II_SEQ_SNE, FrmR, opstr> {
   let TwoOperandAliasConstraint = "$rd = $rs";
 }
@@ -298,7 +299,8 @@ class SetCC64_R<string opstr, PatFrag co
 class SetCC64_I<string opstr, PatFrag cond_op>:
   InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
          !strconcat(opstr, "\t$rt, $rs, $imm10"),
-         [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
+         [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
+                                             immSExt10_64:$imm10)))],
          II_SEQI_SNEI, FrmI, opstr> {
   let TwoOperandAliasConstraint = "$rt = $rs";
 }

Modified: llvm/trunk/test/CodeGen/Mips/octeon.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/octeon.ll?rev=225968&r1=225967&r2=225968&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/octeon.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/octeon.ll Wed Jan 14 04:19:09 2015
@@ -27,3 +27,69 @@ entry:
   %res = mul i64 %a, %b
   ret i64 %res
 }
+
+define i64 @cmpeq(i64 %a, i64 %b) nounwind {
+entry:
+; OCTEON-LABEL: cmpeq:
+; OCTEON: jr     $ra
+; OCTEON: seq    $2, $4, $5
+; MIPS64-LABEL: cmpeq:
+; MIPS64: xor    $1, $4, $5
+; MIPS64: sltiu  $1, $1, 1
+; MIPS64: dsll   $1, $1, 32
+; MIPS64: jr     $ra
+; MIPS64: dsrl   $2, $1, 32
+  %res = icmp eq i64 %a, %b
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}
+
+define i64 @cmpeqi(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: cmpeqi:
+; OCTEON: jr     $ra
+; OCTEON: seqi   $2, $4, 42
+; MIPS64-LABEL: cmpeqi:
+; MIPS64: daddiu $1, $zero, 42
+; MIPS64: xor    $1, $4, $1
+; MIPS64: sltiu  $1, $1, 1
+; MIPS64: dsll   $1, $1, 32
+; MIPS64: jr     $ra
+; MIPS64: dsrl   $2, $1, 32
+  %res = icmp eq i64 %a, 42
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}
+
+define i64 @cmpne(i64 %a, i64 %b) nounwind {
+entry:
+; OCTEON-LABEL: cmpne:
+; OCTEON: jr     $ra
+; OCTEON: sne    $2, $4, $5
+; MIPS64-LABEL: cmpne:
+; MIPS64: xor    $1, $4, $5
+; MIPS64: sltu   $1, $zero, $1
+; MIPS64: dsll   $1, $1, 32
+; MIPS64: jr     $ra
+; MIPS64: dsrl   $2, $1, 32
+  %res = icmp ne i64 %a, %b
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}
+
+define i64 @cmpnei(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: cmpnei:
+; OCTEON: jr     $ra
+; OCTEON: snei   $2, $4, 42
+; MIPS64-LABEL: cmpnei:
+; MIPS64: daddiu $1, $zero, 42
+; MIPS64: xor    $1, $4, $1
+; MIPS64: sltu   $1, $zero, $1
+; MIPS64: dsll   $1, $1, 32
+; MIPS64: jr     $ra
+; MIPS64: dsrl   $2, $1, 32
+  %res = icmp ne i64 %a, 42
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}