[PATCH] AArch64: Relax assert about large shift sizes.

[Matthias Braun]

Shift sizes larger than the size of the value in bits can happen if
constant folding fails.

Testcase based on rdar://19211454

http://reviews.llvm.org/D6940

Files:
  lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  test/CodeGen/AArch64/large_shift.ll

Index: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1424,8 +1424,10 @@
   } else
     return false;
 
-  assert((BiggerPattern || (Srl_imm > 0 && Srl_imm < VT.getSizeInBits())) &&
-         "bad amount in shift node!");
+  // Bail out on large immediates. This happens when no proper
+  // combining/constant folding was performed.
+  if (!BiggerPattern && (Srl_imm <= 0 || Srl_imm >= VT.getSizeInBits()))
+    return false;
 
   LSB = Srl_imm;
   MSB = Srl_imm + (VT == MVT::i32 ? CountTrailingOnes_32(And_imm)
Index: test/CodeGen/AArch64/large_shift.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/large_shift.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=aarch64 -o - %s
+target triple = "arm64-unknown-unknown"
+
+declare void @t()
+
+define void @foo() {
+  %c = bitcast i64 270458 to i64
+  %t0 = lshr i64 %c, 422383
+  %t1 = trunc i64 %t0 to i1
+  br i1 %t1, label %BB1, label %BB0
+
+BB0:
+  call void @t()
+  br label %BB1
+
+BB1:
+  ret void
+}

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