[llvm] r225517 - Assumption that "VectorizedValue" will always be an Instruction is not correct.
Suyog Sarda
suyog.sarda at samsung.com
Fri Jan 9 02:23:48 PST 2015
Author: suyog
Date: Fri Jan 9 04:23:48 2015
New Revision: 225517
URL: http://llvm.org/viewvc/llvm-project?rev=225517&view=rev
Log:
Assumption that "VectorizedValue" will always be an Instruction is not correct.
It can be a constant or a vector argument.
ex :
define i32 @hadd(<4 x i32> %a) #0 {
entry:
%vecext = extractelement <4 x i32> %a, i32 0
%vecext1 = extractelement <4 x i32> %a, i32 1
%add = add i32 %vecext, %vecext1
%vecext2 = extractelement <4 x i32> %a, i32 2
%add3 = add i32 %add, %vecext2
%vecext4 = extractelement <4 x i32> %a, i32 3
%add5 = add i32 %add3, %vecext4
ret i32 %add5
}
Modified:
llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp
Modified: llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp?rev=225517&r1=225516&r2=225517&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp (original)
+++ llvm/trunk/lib/Transforms/Vectorize/SLPVectorizer.cpp Fri Jan 9 04:23:48 2015
@@ -3502,11 +3502,10 @@ private:
/// \brief Emit a horizontal reduction of the vectorized value.
Value *emitReduction(Value *VectorizedValue, IRBuilder<> &Builder) {
assert(VectorizedValue && "Need to have a vectorized tree node");
- Instruction *ValToReduce = dyn_cast<Instruction>(VectorizedValue);
assert(isPowerOf2_32(ReduxWidth) &&
"We only handle power-of-two reductions for now");
- Value *TmpVec = ValToReduce;
+ Value *TmpVec = VectorizedValue;
for (unsigned i = ReduxWidth / 2; i != 0; i >>= 1) {
if (IsPairwiseReduction) {
Value *LeftMask =
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