[PATCH][mips] Refine octeon instructions seq/seqi/sne/snei

[Kai Nacke]

Hello Daniel!

The attached patch refines the pattern for the octeon seq/seqi/sne/snei 
instructions.
The target register is set to 0 or 1 according to the result of the 
comparison. In C, this is something like

rd = (long)(rs == rt)

The attached patch adds a zext to bring the result to i64. With this 
change the instruction is selected for this type of code. (This is the 
same which gcc produces for the C code.)

Please review.

Regards,
Kai

-------------- next part --------------
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 4e2dcd8..bfe2ba0 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -290,7 +290,8 @@ class ExtsCins<string opstr, SDPatternOperator Op = null_frag>:
 class SetCC64_R<string opstr, PatFrag cond_op> :
   InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt),
          !strconcat(opstr, "\t$rd, $rs, $rt"),
-         [(set GPR64Opnd:$rd, (cond_op GPR64Opnd:$rs, GPR64Opnd:$rt))],
+         [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
+                                             GPR64Opnd:$rt)))],
          II_SEQ_SNE, FrmR, opstr> {
   let TwoOperandAliasConstraint = "$rd = $rs";
 }
@@ -298,7 +299,8 @@ class SetCC64_R<string opstr, PatFrag cond_op> :
 class SetCC64_I<string opstr, PatFrag cond_op>:
   InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10),
          !strconcat(opstr, "\t$rt, $rs, $imm10"),
-         [(set GPR64Opnd:$rt, (cond_op GPR64Opnd:$rs, immSExt10_64:$imm10))],
+         [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
+                                             immSExt10_64:$imm10)))],
          II_SEQI_SNEI, FrmI, opstr> {
   let TwoOperandAliasConstraint = "$rt = $rs";
 }
diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll
index d5ff9bd..cd5c89e 100644
--- a/test/CodeGen/Mips/octeon.ll
+++ b/test/CodeGen/Mips/octeon.ll
@@ -27,3 +27,69 @@ entry:
   %res = mul i64 %a, %b
   ret i64 %res
 }
+
+define i64 @cmpeq(i64 %a, i64 %b) nounwind {
+entry:
+; OCTEON-LABEL: cmpeq:
+; OCTEON: jr    $ra
+; OCTEON: seq   $2, $4, $5
+; MIPS64-LABEL: cmpeq:
+; MIPS64: xor
+; MIPS64: sltiu
+; MIPS64: dsll
+; MIPS64: jr
+; MIPS64: dsrl
+  %res = icmp eq i64 %a, %b
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}
+
+define i64 @cmpeqi(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: cmpeqi:
+; OCTEON: jr    $ra
+; OCTEON: seqi  $2, $4, 42
+; MIPS64-LABEL: cmpeqi:
+; MIPS64: daddiu
+; MIPS64: xor
+; MIPS64: sltiu
+; MIPS64: dsll
+; MIPS64: jr
+; MIPS64: dsrl
+  %res = icmp eq i64 %a, 42
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}
+
+define i64 @cmpne(i64 %a, i64 %b) nounwind {
+entry:
+; OCTEON-LABEL: cmpne:
+; OCTEON: jr    $ra
+; OCTEON: sne   $2, $4, $5
+; MIPS64-LABEL: cmpne:
+; MIPS64: xor
+; MIPS64: sltu
+; MIPS64: dsll
+; MIPS64: jr
+; MIPS64: dsrl
+  %res = icmp ne i64 %a, %b
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}
+
+define i64 @cmpnei(i64 %a) nounwind {
+entry:
+; OCTEON-LABEL: cmpnei:
+; OCTEON: jr    $ra
+; OCTEON: snei  $2, $4, 42
+; MIPS64-LABEL: cmpnei:
+; MIPS64: daddiu
+; MIPS64: xor
+; MIPS64: sltu
+; MIPS64: dsll
+; MIPS64: jr
+; MIPS64: dsrl
+  %res = icmp ne i64 %a, 42
+  %res2 = zext i1 %res to i64
+  ret i64 %res2
+}