[llvm] r225374 - [Hexagon] Adding floating point classification and creation.

[Colin LeMahieu]

Author: colinl
Date: Wed Jan  7 14:28:57 2015
New Revision: 225374

URL: http://llvm.org/viewvc/llvm-project?rev=225374&view=rev
Log:
[Hexagon] Adding floating point classification and creation.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
    llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td?rev=225374&r1=225373&r2=225374&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td Wed Jan  7 14:28:57 2015
@@ -437,6 +437,51 @@ def F2_sffma_sc: MInst <
     let Inst{4-0}   = Rx;
   }
 
+// Classify floating-point value
+let Uses = [USR], isFP = 1, isCodeGenOnly = 0 in
+ def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
+
+let Uses = [USR], isFP = 1, isCodeGenOnly = 0 in
+def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
+  "$Pd = dfclass($Rss, #$u5)",
+  [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
+    bits<2> Pd;
+    bits<5> Rss;
+    bits<5> u5;
+
+    let IClass = 0b1101;
+    let Inst{27-21} = 0b1100100;
+    let Inst{20-16} = Rss;
+    let Inst{12-10} = 0b000;
+    let Inst{9-5}   = u5;
+    let Inst{4-3}   = 0b10;
+    let Inst{1-0}   = Pd;
+  }
+
+// Instructions to create floating point constant
+let hasNewValue = 1, opNewValue = 0 in
+class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
+  : ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
+  "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
+  [], "", ALU64_tc_3x_SLOT23>, Requires<[HasV5T]> {
+    bits<5> dst;
+    bits<10> src;
+
+    let IClass = 0b1101;
+    let Inst{27-24} = RegType;
+    let Inst{23}    = 0b0;
+    let Inst{22}    = isNeg;
+    let Inst{21}    = src{9};
+    let Inst{13-5}  = src{8-0};
+    let Inst{4-0}   = dst;
+  }
+
+let isCodeGenOnly = 0 in {
+def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>;
+def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>;
+def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>;
+def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
+}
 
 // Convert single precision to double precision and vice-versa.
 def CONVERT_sf2df : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src),

Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt?rev=225374&r1=225373&r2=225374&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_fp.txt Wed Jan  7 14:28:57 2015
@@ -2,6 +2,10 @@
 
 0x11 0xdf 0x15 0xeb
 # CHECK: r17 = sfadd(r21, r31)
+0x03 0xd5 0xf1 0x85
+# CHECK: p3 = sfclass(r17, #21)
+0xb3 0xc2 0x90 0xdc
+# CHECK: p3 = dfclass(r17:16, #21)
 0x03 0xd5 0xf1 0xc7
 # CHECK: p3 = sfcmp.ge(r17, r21)
 0x23 0xd5 0xf1 0xc7
@@ -86,6 +90,14 @@
 # CHECK: r17 += sfmpy(r21, r31):lib
 0xf1 0xdf 0x15 0xef
 # CHECK: r17 -= sfmpy(r21, r31):lib
+0xb1 0xc2 0x00 0xd6
+# CHECK: r17 = sfmake(#21):pos
+0xb1 0xc2 0x40 0xd6
+# CHECK: r17 = sfmake(#21):neg
+0xb0 0xc2 0x00 0xd9
+# CHECK: r17:16 = dfmake(#21):pos
+0xb0 0xc2 0x40 0xd9
+# CHECK: r17:16 = dfmake(#21):neg
 0x11 0xdf 0x95 0xeb
 # CHECK: r17 = sfmax(r21, r31)
 0x31 0xdf 0x95 0xeb