[llvm] r225344 - [X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. There is no handling for them.

[Craig Topper]

Author: ctopper
Date: Wed Jan  7 02:10:36 2015
New Revision: 225344

URL: http://llvm.org/viewvc/llvm-project?rev=225344&view=rev
Log:
[X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. There is no handling for them.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td

Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=225344&r1=225343&r2=225344&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Wed Jan  7 02:10:36 2015
@@ -49,6 +49,7 @@ def SHL64ri  : RIi8<0xC1, MRM4r, (outs G
                     "shl{q}\t{$src2, $dst|$dst, $src2}",
                     [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
                     IIC_SR>;
+} // isConvertibleToThreeAddress = 1
 
 // NOTE: We don't include patterns for shifts of a register by one, because
 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
@@ -62,7 +63,6 @@ def SHL32r1  : I<0xD1, MRM4r, (outs GR32
 def SHL64r1  : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
                  "shl{q}\t$dst", [], IIC_SR>;
 } // hasSideEffects = 0
-} // isConvertibleToThreeAddress = 1
 } // Constraints = "$src = $dst", SchedRW