[llvm] r225283 - [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
Colin LeMahieu
colinl at codeaurora.org
Tue Jan 6 11:03:20 PST 2015
Author: colinl
Date: Tue Jan 6 13:03:20 2015
New Revision: 225283
URL: http://llvm.org/viewvc/llvm-project?rev=225283&view=rev
Log:
[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
llvm/trunk/lib/Target/Hexagon/HexagonOperands.td
llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt
llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=225283&r1=225282&r2=225283&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Tue Jan 6 13:03:20 2015
@@ -68,7 +68,8 @@ bool isPositiveHalfWord(SDNode *N);
WrapperShuffOB,
WrapperShuffOH,
TC_RETURN,
- EH_RETURN
+ EH_RETURN,
+ DCFETCH
};
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=225283&r1=225282&r2=225283&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Tue Jan 6 13:03:20 2015
@@ -4120,3 +4120,95 @@ def : Pat<(i32 (load FoldGlobalAddrGP:$a
def : Pat<(atomic_load_32 FoldGlobalAddrGP:$addr),
(i32 (L4_loadri_abs FoldGlobalAddrGP:$addr))>,
Requires<[HasV4T]>;
+
+//===----------------------------------------------------------------------===//
+// :raw for of boundscheck:hi:lo insns
+//===----------------------------------------------------------------------===//
+
+// A4_boundscheck_lo: Detect if a register is within bounds.
+let hasSideEffects = 0, isCodeGenOnly = 0 in
+def A4_boundscheck_lo: ALU64Inst <
+ (outs PredRegs:$Pd),
+ (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
+ "$Pd = boundscheck($Rss, $Rtt):raw:lo"> {
+ bits<2> Pd;
+ bits<5> Rss;
+ bits<5> Rtt;
+
+ let IClass = 0b1101;
+
+ let Inst{27-23} = 0b00100;
+ let Inst{13} = 0b1;
+ let Inst{7-5} = 0b100;
+ let Inst{1-0} = Pd;
+ let Inst{20-16} = Rss;
+ let Inst{12-8} = Rtt;
+ }
+
+// A4_boundscheck_hi: Detect if a register is within bounds.
+let hasSideEffects = 0, isCodeGenOnly = 0 in
+def A4_boundscheck_hi: ALU64Inst <
+ (outs PredRegs:$Pd),
+ (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
+ "$Pd = boundscheck($Rss, $Rtt):raw:hi"> {
+ bits<2> Pd;
+ bits<5> Rss;
+ bits<5> Rtt;
+
+ let IClass = 0b1101;
+
+ let Inst{27-23} = 0b00100;
+ let Inst{13} = 0b1;
+ let Inst{7-5} = 0b101;
+ let Inst{1-0} = Pd;
+ let Inst{20-16} = Rss;
+ let Inst{12-8} = Rtt;
+ }
+
+let hasSideEffects = 0 in
+def A4_boundscheck : MInst <
+ (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
+ "$Pd=boundscheck($Rs,$Rtt)">;
+
+// A4_tlbmatch: Detect if a VA/ASID matches a TLB entry.
+let isPredicateLate = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
+def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd),
+ (ins DoubleRegs:$Rs, IntRegs:$Rt),
+ "$Pd = tlbmatch($Rs, $Rt)",
+ [], "", ALU64_tc_2early_SLOT23> {
+ bits<2> Pd;
+ bits<5> Rs;
+ bits<5> Rt;
+
+ let IClass = 0b1101;
+ let Inst{27-23} = 0b00100;
+ let Inst{20-16} = Rs;
+ let Inst{13} = 0b1;
+ let Inst{12-8} = Rt;
+ let Inst{7-5} = 0b011;
+ let Inst{1-0} = Pd;
+ }
+
+// We need custom lowering of ISD::PREFETCH into HexagonISD::DCFETCH
+// because the SDNode ISD::PREFETCH has properties MayLoad and MayStore.
+// We don't really want either one here.
+def SDTHexagonDCFETCH : SDTypeProfile<0, 2, [SDTCisPtrTy<0>,SDTCisInt<1>]>;
+def HexagonDCFETCH : SDNode<"HexagonISD::DCFETCH", SDTHexagonDCFETCH,
+ [SDNPHasChain]>;
+
+// Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't
+// really do a load.
+let hasSideEffects = 1, mayLoad = 0, isCodeGenOnly = 0 in
+def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3),
+ "dcfetch($Rs + #$u11_3)",
+ [(HexagonDCFETCH IntRegs:$Rs, u11_3ImmPred:$u11_3)],
+ "", LD_tc_ld_SLOT0> {
+ bits<5> Rs;
+ bits<14> u11_3;
+
+ let IClass = 0b1001;
+ let Inst{27-21} = 0b0100000;
+ let Inst{20-16} = Rs;
+ let Inst{13} = 0b0;
+ let Inst{10-0} = u11_3{13-3};
+}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOperands.td?rev=225283&r1=225282&r2=225283&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOperands.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOperands.td Tue Jan 6 13:03:20 2015
@@ -259,6 +259,13 @@ def u16_s8ImmPred : PatLeaf<(i32 imm),
return isShiftedUInt<16,8>(v);
}]>;
+def u11_3ImmPred : PatLeaf<(i32 imm), [{
+ // True if the immediate fits in a 14-bit unsigned field, and the lowest
+ // three bits are 0.
+ int64_t v = (int64_t)N->getSExtValue();
+ return isShiftedUInt<11,3>(v);
+}]>;
+
def u9ImmPred : PatLeaf<(i32 imm), [{
// u9ImmPred predicate - True if the immediate fits in a 9-bit unsigned
// field.
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt?rev=225283&r1=225282&r2=225283&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/system_user.txt Tue Jan 6 13:03:20 2015
@@ -6,5 +6,7 @@
# CHECK: r17:16 = memd_locked(r21)
0x00 0xc0 0x00 0xa8
# CHECK: barrier
+0x15 0xc0 0x11 0x94
+# CHECK: dcfetch(r17 + #168)
0x00 0xc0 0x51 0x62
# CHECK: trace(r17)
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt?rev=225283&r1=225282&r2=225283&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/xtype_pred.txt Tue Jan 6 13:03:20 2015
@@ -1,5 +1,9 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
+0x83 0xf4 0x10 0xd2
+# CHECK: p3 = boundscheck(r17:16, r21:20):raw:lo
+0xa3 0xf4 0x10 0xd2
+# CHECK: p3 = boundscheck(r17:16, r21:20):raw:hi
0x43 0xd5 0xd1 0xc7
# CHECK: p3 = cmpb.gt(r17, r21)
0xc3 0xd5 0xd1 0xc7
@@ -44,6 +48,8 @@
# CHECK: p3 = !bitsclr(r17, r21)
0x10 0xc3 0x00 0x86
# CHECK: r17:16 = mask(p3)
+0x63 0xf5 0x10 0xd2
+# CHECK: p3 = tlbmatch(r17:16, r21)
0x03 0xc0 0x45 0x85
# CHECK: p3 = r5
0x05 0xc0 0x43 0x89
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