[llvm] r225189 - [PowerPC] Remove zexts after byte-swapping loads
Hal Finkel
hfinkel at anl.gov
Mon Jan 5 10:09:06 PST 2015
Author: hfinkel
Date: Mon Jan 5 12:09:06 2015
New Revision: 225189
URL: http://llvm.org/viewvc/llvm-project?rev=225189&view=rev
Log:
[PowerPC] Remove zexts after byte-swapping loads
lhbrx and lwbrx not only load their data with byte swapping, but also clear the
upper 32 bits (at least). As a result, they can be added to the PPCISelDAGToDAG
peephole optimization as frontier instructions for the removal of unnecessary
zero extensions.
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/test/CodeGen/PowerPC/rm-zext.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=225189&r1=225188&r2=225189&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Jan 5 12:09:06 2015
@@ -3729,6 +3729,13 @@ static bool PeepholePPC64ZExtGather(SDVa
return true;
}
+ // LHBRX and LWBRX always clear the higher-order bits.
+ if (Op32.getMachineOpcode() == PPC::LHBRX ||
+ Op32.getMachineOpcode() == PPC::LWBRX) {
+ ToPromote.insert(Op32.getNode());
+ return true;
+ }
+
// Next, check for those instructions we can look through.
// Assuming the mask does not wrap around, then the higher-order bits are
@@ -3916,6 +3923,8 @@ void PPCDAGToDAGISel::PeepholePPC64ZExt(
case PPC::SRW: NewOpcode = PPC::SRW8; break;
case PPC::LI: NewOpcode = PPC::LI8; break;
case PPC::LIS: NewOpcode = PPC::LIS8; break;
+ case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
+ case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
case PPC::OR: NewOpcode = PPC::OR8; break;
case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=225189&r1=225188&r2=225189&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Mon Jan 5 12:09:06 2015
@@ -843,6 +843,13 @@ def LDBRX : XForm_1<31, 532, (outs g8rc
"ldbrx $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
+let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in {
+def LHBRX8 : XForm_1<31, 790, (outs g8rc:$rD), (ins memrr:$src),
+ "lhbrx $rD, $src", IIC_LdStLoad, []>;
+def LWBRX8 : XForm_1<31, 534, (outs g8rc:$rD), (ins memrr:$src),
+ "lwbrx $rD, $src", IIC_LdStLoad, []>;
+}
+
let mayLoad = 1, hasSideEffects = 0 in {
def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
"ldu $rD, $addr", IIC_LdStLDU,
Modified: llvm/trunk/test/CodeGen/PowerPC/rm-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/rm-zext.ll?rev=225189&r1=225188&r2=225189&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/rm-zext.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/rm-zext.ll Mon Jan 5 12:09:06 2015
@@ -39,5 +39,35 @@ entry:
; CHECK: blr
}
+; Function Attrs: nounwind readnone
+declare i32 @llvm.bswap.i32(i32) #1
+
+; Function Attrs: nounwind readonly
+define zeroext i32 @bs32(i32* nocapture readonly %x) #0 {
+entry:
+ %0 = load i32* %x, align 4
+ %1 = tail call i32 @llvm.bswap.i32(i32 %0)
+ ret i32 %1
+
+; CHECK-LABEL: @bs32
+; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readonly
+define zeroext i16 @bs16(i16* nocapture readonly %x) #0 {
+entry:
+ %0 = load i16* %x, align 2
+ %1 = tail call i16 @llvm.bswap.i16(i16 %0)
+ ret i16 %1
+
+; CHECK-LABEL: @bs16
+; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
+; CHECK: blr
+}
+
+; Function Attrs: nounwind readnone
+declare i16 @llvm.bswap.i16(i16) #1
+
attributes #0 = { nounwind readnone }
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