[PATCH] [AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.

[James Molloy]

LGTM!


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Comment at: lib/Target/AArch64/AArch64InstrInfo.td:1894
@@ +1893,3 @@
+multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
+                                 ValueType VecTy, ValueType STy,
+                                 SubRegIndex SubRegIdx,
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There looks to be an indentation problem here.

http://reviews.llvm.org/D6772

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