[llvm] r224867 - [Hexagon] Adding post-increment unsigned byte loads.
Colin LeMahieu
colinl at codeaurora.org
Fri Dec 26 11:12:12 PST 2014
Author: colinl
Date: Fri Dec 26 13:12:11 2014
New Revision: 224867
URL: http://llvm.org/viewvc/llvm-project?rev=224867&view=rev
Log:
[Hexagon] Adding post-increment unsigned byte loads.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=224867&r1=224866&r2=224867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Fri Dec 26 13:12:11 2014
@@ -610,7 +610,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndex
Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
} else if (LoadedVT == MVT::i8) {
if (TII->isValidAutoIncImm(LoadedVT, Val))
- Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::L2_loadrb_pi;
+ Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
else
Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
} else
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=224867&r1=224866&r2=224867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Fri Dec 26 13:12:11 2014
@@ -695,7 +695,7 @@ bool HexagonInstrInfo::isPredicable(Mach
return isShiftedInt<4,1>(MI->getOperand(3).getImm());
case Hexagon::L2_loadrb_pi:
- case Hexagon::POST_LDriub:
+ case Hexagon::L2_loadrub_pi:
return isInt<4>(MI->getOperand(3).getImm());
case Hexagon::STrib_imm_V4:
@@ -1367,8 +1367,8 @@ isConditionalLoad (const MachineInstr* M
case Hexagon::L2_ploadrbf_pi :
case Hexagon::POST_LDriuh_cPt :
case Hexagon::POST_LDriuh_cNotPt :
- case Hexagon::POST_LDriub_cPt :
- case Hexagon::POST_LDriub_cNotPt :
+ case Hexagon::L2_ploadrubt_pi :
+ case Hexagon::L2_ploadrubf_pi :
return QRI.Subtarget.hasV4TOps();
case Hexagon::LDrid_indexed_shl_cPt_V4 :
case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=224867&r1=224866&r2=224867&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Fri Dec 26 13:12:11 2014
@@ -1698,6 +1698,7 @@ multiclass LD_PostInc <string mnemonic,
// post increment byte loads with immediate offset
let accessSize = ByteAccess, isCodeGenOnly = 0 in {
defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>;
+ defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>;
}
multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
@@ -1740,8 +1741,6 @@ multiclass LD_PostInc2<string mnemonic,
}
let hasCtrlDep = 1, hasSideEffects = 0, addrMode = PostInc in {
- defm POST_LDriub : LD_PostInc2<"memub", "LDriub", IntRegs, s4_0Imm>,
- PredNewRel;
defm POST_LDrih : LD_PostInc2<"memh", "LDrih", IntRegs, s4_1Imm>,
PredNewRel;
defm POST_LDriuh : LD_PostInc2<"memuh", "LDriuh", IntRegs, s4_1Imm>,
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=224867&r1=224866&r2=224867&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt Fri Dec 26 13:12:11 2014
@@ -13,6 +13,8 @@
0xf1 0xc3 0x15 0x91
# CHECK: r17 = memb(r21 + #31)
+0xb1 0xc0 0x15 0x9b
+# CHECK: r17 = memb(r21++#5)
0x91 0xdd 0x15 0x41
# CHECK: if (p3) r17 = memb(r21 + #44)
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x43
@@ -23,14 +25,24 @@
0x03 0x40 0x45 0x85 0x91 0xdd 0x15 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memb(r21 + #44)
+0xb1 0xe6 0x15 0x9b
+# CHECK: if (p3) r17 = memb(r21++#5)
+0xb1 0xee 0x15 0x9b
+# CHECK: if (!p3) r17 = memb(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xf6 0x15 0x9b
+# CHECK: p3 = r5
+# CHECK-NEXT: if (p3.new) r17 = memb(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xfe 0x15 0x9b
+# CHECK: p3 = r5
+# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
0xf1 0xc3 0x55 0x91
# CHECK: r17 = memh(r21 + #62)
0xf1 0xc3 0x35 0x91
# CHECK: r17 = memub(r21 + #31)
-0xb1 0xc0 0x15 0x9b
-# CHECK: r17 = memb(r21++#5)
+0xb1 0xc0 0x35 0x9b
+# CHECK: r17 = memub(r21++#5)
0xf1 0xdb 0x35 0x41
# CHECK: if (p3) r17 = memub(r21 + #31)
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x43
@@ -41,16 +53,16 @@
0x03 0x40 0x45 0x85 0xf1 0xdb 0x35 0x47
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = memub(r21 + #31)
-0xb1 0xe6 0x15 0x9b
-# CHECK: if (p3) r17 = memb(r21++#5)
-0xb1 0xee 0x15 0x9b
-# CHECK: if (!p3) r17 = memb(r21++#5)
-0x03 0x40 0x45 0x85 0xb1 0xf6 0x15 0x9b
+0xb1 0xe6 0x35 0x9b
+# CHECK: if (p3) r17 = memub(r21++#5)
+0xb1 0xee 0x35 0x9b
+# CHECK: if (!p3) r17 = memub(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xf6 0x35 0x9b
# CHECK: p3 = r5
-# CHECK-NEXT: if (p3.new) r17 = memb(r21++#5)
-0x03 0x40 0x45 0x85 0xb1 0xfe 0x15 0x9b
+# CHECK-NEXT: if (p3.new) r17 = memub(r21++#5)
+0x03 0x40 0x45 0x85 0xb1 0xfe 0x35 0x9b
# CHECK: p3 = r5
-# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
+# CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5)
0xb1 0xc2 0x75 0x91
# CHECK: r17 = memuh(r21 + #42)
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